Lines Matching +full:bank +full:- +full:number

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
31 /* All Banks, Offset 0xe: Bank Select Register */
33 #define	BSR_BANK_MASK		0x0007	/* Which bank is currently selected */
37 /* Bank 0, Offset 0x0: Transmit Control Register */
50 /* Bank 0, Offset 0x2: EPH Status Register */
67 /* Bank 0, Offset 0x4: Receive Control Register */
78 /* Bank 0, Offset 0x6: Counter Register */
89 /* Bank 0, Offset 0x8: Memory Information Register */
97 /* Bank 0, Offset 0xa: Receive/PHY Control Reigster */
100 #define	RPCR_DPLX		0x1000	/* Put PHY in full-duplex mode */
108 #define	RPCR_LED_LINK_FDX	0x3	/* Full-duplex link detected */
114 /* Bank 1, Offset 0x0: Configuration Register */
121 /* Bank 1, Offset 0x2: Base Address Register */
129 /* Bank 1, Offsets 0x4: Individual Address Registers */
137 /* Bank 1, Offset 0xa: General Purpose Register */
140 /* Bank 1, Offset 0xc: Control Register */
151 /* Bank 2, Offset 0x0: MMU Command Register */
163 /* Bank 2, Offset 0x2: Packet Number Register */
167 /* Bank 2, Offset 0x3: Allocation Result Register */
172 /* Bank 2, Offset 0x4: FIFO Ports Register */
176 #define	FIFO_PACKET_MASK	0x3f	/* Packet number mask */
178 /* Bank 2, Offset 0x6: Pointer Register */
187 /* Bank 2, Offset 0x8: Data Registers */
191 /* Bank 2, Offset 0xc: Interrupt Status Registers */
208 /* Bank 3, Offset 0x0: Multicast Table Registers */
211 /* Bank 3, Offset 0x8: Management Interface */
219 /* Bank 3, Offset 0xa: Revision Register */
234 /* Bank 3, Offset 0xc: Early RCV Register */
249 #define	RX_ODDFRM		0x1000	/* Frame has odd number of bytes */
258 /* Number of times to spin on TX allocations */