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/linux/Documentation/devicetree/bindings/spi/
H A Dadi,axi-spi-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI SPI Engine Controller
10 The AXI SPI Engine controller is part of the SPI Engine framework[1] and
11 allows memory mapped access to the SPI Engine control bus. This allows it
12 to be used as a general purpose software driven SPI controller as well as
15 [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine
18 - Michael Hennerich <Michael.Hennerich@analog.com>
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/linux/drivers/spi/
H A Dspi-axi-spi-engine.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI-Engine SPI controller driver
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
10 #include <linux/fpga/adi-axi-common.h>
17 #include <linux/spi/spi.h>
18 #include <trace/events/spi.h>
38 #define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
43 #define SPI_ENGINE_CONFIG_CPOL BIT(1)
63 /* Arbitrary sync ID for use by host->cur_msg */
88 * struct spi_engine_message_state - SPI engine per-message state
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
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/linux/drivers/iio/adc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 bool "ST-Ericsson AB8500 GPADC driver"
26 depends on SPI
31 SPI analog to digital converters (ADC).
38 depends on SPI
45 Say yes here to build support for Analog Devices AD4130-8 SPI analog
53 depends on SPI
73 Say yes here to build support for Analog Devices AD7091R-5 ADC.
77 depends on SPI
81 Say yes here to build support for Analog Devices AD7091R-2, AD7091R-4,
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/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt8188.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
15 #include <dt-bindings/power/mediatek,mt8188-power.h>
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H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
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H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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H A Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm8550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
[all …]
H A Dsm8650.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
[all …]
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
26 * 1. Host is protected by:
27 * - Range registers
28 * - MMU
31 * - Range registers (protect the first 512MB)
34 * - Range registers
35 * - Protection bits
39 * QMAN DMA channels 0,1 (PCI DMAN):
40 * - DMA is not secured.
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/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2020-2022 HabanaLabs, Ltd.
32 #define GAUDI2_RESET_WAIT_MSEC 1 /* 1ms */
34 #define GAUDI2_PLDM_RESET_WAIT_MSEC 1000 /* 1s */
40 #define GAUDI2_PLDM_TEST_QUEUE_WAIT_USEC 1000000 /* 1s */
45 * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs
49 #define MAX_CLUSTER_BINNING_FAULTY_TPCS 1
50 #define MAX_FAULTY_XBARS 1
51 #define MAX_FAULTY_EDMAS 1
52 #define MAX_FAULTY_DECODERS 1
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