1 // SPDX-License-Identifier: GPL-2.0
3  * AD7606 SPI ADC driver
44  * X is the integer part and X + 1 is the fractional part.
83 	{ 0, 610352 }, { 1, 220703 }
91 	1, 2, 4, 8, 16, 32, 64,
95 	1, 2, 4, 8, 16, 32, 64, 128, 256,
99 	1, 2, 4, 8, 16, 32, 64, 128,
103 	-128, 1, 127,
107 	-512, 4, 508,
135 	.name = "ad7605-4",
144 	.name = "ad7606-8",
155 	.name = "ad7606-6",
167 	.name = "ad7606-4",
194 	.max_samplerate = 1 * MEGA,
246 	.max_samplerate = 1 * MEGA,
262 	.max_samplerate = 1 * MEGA,
278 	if (st->gpio_reset) {  in ad7606_reset()
279 		gpiod_set_value(st->gpio_reset, 1);  in ad7606_reset()
281 		gpiod_set_value(st->gpio_reset, 0);  in ad7606_reset()
285 	return -ENODEV;  in ad7606_reset()
293 	struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];  in ad7606_16bit_chan_scale_setup()
295 	if (!st->sw_mode_en) {  in ad7606_16bit_chan_scale_setup()
296 		/* tied to logic low, analog input range is +/- 5V */  in ad7606_16bit_chan_scale_setup()
297 		ci->range = 0;  in ad7606_16bit_chan_scale_setup()
298 		ci->scale_avail = ad7606_16bit_hw_scale_avail;  in ad7606_16bit_chan_scale_setup()
299 		ci->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail);  in ad7606_16bit_chan_scale_setup()
305 	ci->range = 2;  in ad7606_16bit_chan_scale_setup()
306 	ci->scale_avail = ad7606_16bit_sw_scale_avail;  in ad7606_16bit_chan_scale_setup()
307 	ci->num_scales = ARRAY_SIZE(ad7606_16bit_sw_scale_avail);  in ad7606_16bit_chan_scale_setup()
317 	unsigned int num_channels = st->chip_info->num_adc_channels;  in ad7606_get_chan_config()
318 	struct device *dev = st->dev;  in ad7606_get_chan_config()
332 		/* channel number (here) is from 1 to num_channels */  in ad7606_get_chan_config()
333 		if (reg < 1 || reg > num_channels)  in ad7606_get_chan_config()
334 			return -EINVAL;  in ad7606_get_chan_config()
337 		if (reg != (ch + 1))  in ad7606_get_chan_config()
342 		ret = fwnode_property_read_u32_array(child, "diff-channels",  in ad7606_get_chan_config()
345 		if (ret == 0 && (pins[0] != reg || pins[1] != reg)) {  in ad7606_get_chan_config()
348 			return -EINVAL;  in ad7606_get_chan_config()
357 			return -EINVAL;  in ad7606_get_chan_config()
360 		ci = &st->chan_info[reg - 1];  in ad7606_get_chan_config()
362 		ci->r_gain = 0;  in ad7606_get_chan_config()
363 		ret = fwnode_property_read_u32(child, "adi,rfilter-ohms",  in ad7606_get_chan_config()
364 					       &ci->r_gain);  in ad7606_get_chan_config()
365 		if (ret == 0 && ci->r_gain > AD7606_CALIB_GAIN_MAX)  in ad7606_get_chan_config()
366 			return -EINVAL;  in ad7606_get_chan_config()
378 	struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];  in ad7606c_18bit_chan_scale_setup()
382 	if (!st->sw_mode_en) {  in ad7606c_18bit_chan_scale_setup()
383 		ci->range = 0;  in ad7606c_18bit_chan_scale_setup()
384 		ci->scale_avail = ad7606_18bit_hw_scale_avail;  in ad7606c_18bit_chan_scale_setup()
385 		ci->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail);  in ad7606c_18bit_chan_scale_setup()
389 	ret = ad7606_get_chan_config(indio_dev, chan->scan_index, &bipolar,  in ad7606c_18bit_chan_scale_setup()
395 		ci->scale_avail = ad7606c_18bit_differential_bipolar_scale_avail;  in ad7606c_18bit_chan_scale_setup()
396 		ci->num_scales =  in ad7606c_18bit_chan_scale_setup()
399 		ci->reg_offset = 8;  in ad7606c_18bit_chan_scale_setup()
400 		ci->range = 1;  in ad7606c_18bit_chan_scale_setup()
401 		chan->differential = 1;  in ad7606c_18bit_chan_scale_setup()
402 		chan->channel2 = chan->channel;  in ad7606c_18bit_chan_scale_setup()
407 	chan->differential = 0;  in ad7606c_18bit_chan_scale_setup()
410 		ci->scale_avail = ad7606c_18bit_single_ended_bipolar_scale_avail;  in ad7606c_18bit_chan_scale_setup()
411 		ci->num_scales =  in ad7606c_18bit_chan_scale_setup()
413 		/* Bipolar single-ended ranges start at 0 (b0000) */  in ad7606c_18bit_chan_scale_setup()
414 		ci->reg_offset = 0;  in ad7606c_18bit_chan_scale_setup()
415 		ci->range = 3;  in ad7606c_18bit_chan_scale_setup()
416 		chan->scan_type.sign = 's';  in ad7606c_18bit_chan_scale_setup()
421 	ci->scale_avail = ad7606c_18bit_single_ended_unipolar_scale_avail;  in ad7606c_18bit_chan_scale_setup()
422 	ci->num_scales =  in ad7606c_18bit_chan_scale_setup()
424 	/* Unipolar single-ended ranges start at 5 (b0101) */  in ad7606c_18bit_chan_scale_setup()
425 	ci->reg_offset = 5;  in ad7606c_18bit_chan_scale_setup()
426 	ci->range = 1;  in ad7606c_18bit_chan_scale_setup()
427 	chan->scan_type.sign = 'u';  in ad7606c_18bit_chan_scale_setup()
436 	struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];  in ad7606c_16bit_chan_scale_setup()
440 	if (!st->sw_mode_en) {  in ad7606c_16bit_chan_scale_setup()
441 		ci->range = 0;  in ad7606c_16bit_chan_scale_setup()
442 		ci->scale_avail = ad7606_16bit_hw_scale_avail;  in ad7606c_16bit_chan_scale_setup()
443 		ci->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail);  in ad7606c_16bit_chan_scale_setup()
447 	ret = ad7606_get_chan_config(indio_dev, chan->scan_index, &bipolar,  in ad7606c_16bit_chan_scale_setup()
453 		ci->scale_avail = ad7606c_16bit_differential_bipolar_scale_avail;  in ad7606c_16bit_chan_scale_setup()
454 		ci->num_scales =  in ad7606c_16bit_chan_scale_setup()
457 		ci->reg_offset = 8;  in ad7606c_16bit_chan_scale_setup()
458 		ci->range = 1;  in ad7606c_16bit_chan_scale_setup()
459 		chan->differential = 1;  in ad7606c_16bit_chan_scale_setup()
460 		chan->channel2 = chan->channel;  in ad7606c_16bit_chan_scale_setup()
461 		chan->scan_type.sign = 's';  in ad7606c_16bit_chan_scale_setup()
466 	chan->differential = 0;  in ad7606c_16bit_chan_scale_setup()
469 		ci->scale_avail = ad7606c_16bit_single_ended_bipolar_scale_avail;  in ad7606c_16bit_chan_scale_setup()
470 		ci->num_scales =  in ad7606c_16bit_chan_scale_setup()
472 		/* Bipolar single-ended ranges start at 0 (b0000) */  in ad7606c_16bit_chan_scale_setup()
473 		ci->reg_offset = 0;  in ad7606c_16bit_chan_scale_setup()
474 		ci->range = 3;  in ad7606c_16bit_chan_scale_setup()
475 		chan->scan_type.sign = 's';  in ad7606c_16bit_chan_scale_setup()
480 	ci->scale_avail = ad7606c_16bit_single_ended_unipolar_scale_avail;  in ad7606c_16bit_chan_scale_setup()
481 	ci->num_scales =  in ad7606c_16bit_chan_scale_setup()
483 	/* Unipolar single-ended ranges start at 5 (b0101) */  in ad7606c_16bit_chan_scale_setup()
484 	ci->reg_offset = 5;  in ad7606c_16bit_chan_scale_setup()
485 	ci->range = 1;  in ad7606c_16bit_chan_scale_setup()
486 	chan->scan_type.sign = 'u';  in ad7606c_16bit_chan_scale_setup()
495 	struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];  in ad7607_chan_scale_setup()
497 	ci->range = 0;  in ad7607_chan_scale_setup()
498 	ci->scale_avail = ad7607_hw_scale_avail;  in ad7607_chan_scale_setup()
499 	ci->num_scales = ARRAY_SIZE(ad7607_hw_scale_avail);  in ad7607_chan_scale_setup()
507 	struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];  in ad7608_chan_scale_setup()
509 	ci->range = 0;  in ad7608_chan_scale_setup()
510 	ci->scale_avail = ad7606_18bit_hw_scale_avail;  in ad7608_chan_scale_setup()
511 	ci->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail);  in ad7608_chan_scale_setup()
519 	struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];  in ad7609_chan_scale_setup()
521 	ci->range = 0;  in ad7609_chan_scale_setup()
522 	ci->scale_avail = ad7609_hw_scale_avail;  in ad7609_chan_scale_setup()
523 	ci->num_scales = ARRAY_SIZE(ad7609_hw_scale_avail);  in ad7609_chan_scale_setup()
535 	guard(mutex)(&st->lock);  in ad7606_reg_access()
538 		ret = st->bops->reg_read(st, reg);  in ad7606_reg_access()
544 		return st->bops->reg_write(st, reg, writeval);  in ad7606_reg_access()
553 	pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_pwm_set_high()
557 	ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_pwm_set_high()
567 	pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_pwm_set_low()
571 	ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_pwm_set_low()
581 	pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_pwm_set_swing()
585 	return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_pwm_set_swing()
593 	pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_pwm_is_swinging()
606 		return -EINVAL;  in ad7606_set_sampling_freq()
609 	pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_set_sampling_freq()
621 	return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_set_sampling_freq()
626 	unsigned int num = st->chip_info->num_adc_channels;  in ad7606_read_samples()
628 	return st->bops->read_block(st->dev, num, &st->data);  in ad7606_read_samples()
634 	struct iio_dev *indio_dev = pf->indio_dev;  in ad7606_trigger_handler()
638 	guard(mutex)(&st->lock);  in ad7606_trigger_handler()
644 	iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data),  in ad7606_trigger_handler()
647 	iio_trigger_notify_done(indio_dev->trig);  in ad7606_trigger_handler()
649 	gpiod_set_value(st->gpio_convst, 1);  in ad7606_trigger_handler()
662 	if (st->gpio_convst) {  in ad7606_scan_direct()
663 		gpiod_set_value(st->gpio_convst, 1);  in ad7606_scan_direct()
676 	if (st->trig) {  in ad7606_scan_direct()
677 		ret = wait_for_completion_timeout(&st->completion,  in ad7606_scan_direct()
680 			ret = -ETIMEDOUT;  in ad7606_scan_direct()
696 	chan = &indio_dev->channels[ch];  in ad7606_scan_direct()
697 	realbits = chan->scan_type.realbits;  in ad7606_scan_direct()
700 		*val = st->data.buf32[ch];  in ad7606_scan_direct()
702 		*val = st->data.buf16[ch];  in ad7606_scan_direct()
704 	*val &= GENMASK(realbits - 1, 0);  in ad7606_scan_direct()
706 	if (chan->scan_type.sign == 's')  in ad7606_scan_direct()
707 		*val = sign_extend32(*val, realbits - 1);  in ad7606_scan_direct()
710 	if (!st->gpio_convst) {  in ad7606_scan_direct()
715 	gpiod_set_value(st->gpio_convst, 0);  in ad7606_scan_direct()
724 	ret = st->bops->reg_read(st, AD7606_CALIB_OFFSET(ch));  in ad7606_get_calib_offset()
728 	*val = st->chip_info->calib_offset_avail[0] +  in ad7606_get_calib_offset()
729 	       ret * st->chip_info->calib_offset_avail[1];  in ad7606_get_calib_offset()
739 	ret = st->bops->reg_read(st, AD7606_CALIB_PHASE(ch));  in ad7606_get_calib_phase()
747 	 * ad7606c-16/18: phase delay from 0 µs to 255 µs in steps of 1 µs.  in ad7606_get_calib_phase()
749 	*val2 = ret * st->chip_info->calib_phase_avail[1][1];  in ad7606_get_calib_phase()
768 			return -EBUSY;  in ad7606_read_raw()
769 		ret = ad7606_scan_direct(indio_dev, chan->scan_index, val);  in ad7606_read_raw()
775 		if (st->sw_mode_en)  in ad7606_read_raw()
776 			ch = chan->scan_index;  in ad7606_read_raw()
777 		ci = &st->chan_info[ch];  in ad7606_read_raw()
778 		*val = ci->scale_avail[ci->range][0];  in ad7606_read_raw()
779 		*val2 = ci->scale_avail[ci->range][1];  in ad7606_read_raw()
782 		*val = st->oversampling;  in ad7606_read_raw()
785 		pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);  in ad7606_read_raw()
790 			return -EBUSY;  in ad7606_read_raw()
791 		ret = ad7606_get_calib_offset(st, chan->scan_index, val);  in ad7606_read_raw()
798 			return -EBUSY;  in ad7606_read_raw()
799 		ret = ad7606_get_calib_phase(st, chan->scan_index, val, val2);  in ad7606_read_raw()
805 	return -EINVAL;  in ad7606_read_raw()
814 	struct ad7606_chan_info *ci = &st->chan_info[0];  in in_voltage_scale_available_show()
815 	const unsigned int (*vals)[2] = ci->scale_avail;  in in_voltage_scale_available_show()
819 	for (i = 0; i < ci->num_scales; i++)  in in_voltage_scale_available_show()
820 		len += scnprintf(buf + len, PAGE_SIZE - len, "%u.%06u ",  in in_voltage_scale_available_show()
821 				 vals[i][0], vals[i][1]);  in in_voltage_scale_available_show()
822 	buf[len - 1] = '\n';  in in_voltage_scale_available_show()
833 	gpiod_set_value(st->gpio_range, val);  in ad7606_write_scale_hw()
845 	gpiod_multi_set_value_cansleep(st->gpio_os, values);  in ad7606_write_os_hw()
848 	if (st->chip_info->os_req_reset)  in ad7606_write_os_hw()
859 	start_val = st->chip_info->calib_offset_avail[0];  in ad7606_set_calib_offset()
860 	step_val = st->chip_info->calib_offset_avail[1];  in ad7606_set_calib_offset()
861 	stop_val = st->chip_info->calib_offset_avail[2];  in ad7606_set_calib_offset()
864 		return -EINVAL;  in ad7606_set_calib_offset()
866 	offset = (val - start_val) / step_val;  in ad7606_set_calib_offset()
868 	return st->bops->reg_write(st, AD7606_CALIB_OFFSET(ch), offset);  in ad7606_set_calib_offset()
877 		return -EINVAL;  in ad7606_set_calib_phase()
879 	start_ns = st->chip_info->calib_phase_avail[0][1];  in ad7606_set_calib_phase()
880 	step_ns = st->chip_info->calib_phase_avail[1][1];  in ad7606_set_calib_phase()
881 	stop_ns = st->chip_info->calib_phase_avail[2][1];  in ad7606_set_calib_phase()
885 	 * ad7606c-16/18: phase delay from 0 µs to 255 µs in steps of 1 µs.  in ad7606_set_calib_phase()
888 		return -EINVAL;  in ad7606_set_calib_phase()
892 	return st->bops->reg_write(st, AD7606_CALIB_PHASE(ch), wreg);  in ad7606_set_calib_phase()
908 		return -EINVAL;  in ad7606_write_raw_get_fmt()
923 	guard(mutex)(&st->lock);  in ad7606_write_raw()
927 		if (st->sw_mode_en)  in ad7606_write_raw()
928 			ch = chan->scan_index;  in ad7606_write_raw()
929 		ci = &st->chan_info[ch];  in ad7606_write_raw()
930 		for (i = 0; i < ci->num_scales; i++) {  in ad7606_write_raw()
931 			scale_avail_uv[i] = ci->scale_avail[i][0] * MICRO +  in ad7606_write_raw()
932 					    ci->scale_avail[i][1];  in ad7606_write_raw()
935 		i = find_closest(val, scale_avail_uv, ci->num_scales);  in ad7606_write_raw()
938 			return -EBUSY;  in ad7606_write_raw()
939 		ret = st->write_scale(indio_dev, ch, i + ci->reg_offset);  in ad7606_write_raw()
943 		ci->range = i;  in ad7606_write_raw()
948 			return -EINVAL;  in ad7606_write_raw()
949 		i = find_closest(val, st->oversampling_avail,  in ad7606_write_raw()
950 				 st->num_os_ratios);  in ad7606_write_raw()
953 			return -EBUSY;  in ad7606_write_raw()
954 		ret = st->write_os(indio_dev, i);  in ad7606_write_raw()
958 		st->oversampling = st->oversampling_avail[i];  in ad7606_write_raw()
963 			return -EINVAL;  in ad7606_write_raw()
967 			return -EBUSY;  in ad7606_write_raw()
968 		ret = ad7606_set_calib_offset(st, chan->scan_index, val);  in ad7606_write_raw()
973 			return -EBUSY;  in ad7606_write_raw()
974 		ret = ad7606_set_calib_phase(st, chan->scan_index, val, val2);  in ad7606_write_raw()
978 		return -EINVAL;  in ad7606_write_raw()
988 	const unsigned int *vals = st->oversampling_avail;  in ad7606_oversampling_ratio_avail()
992 	for (i = 0; i < st->num_os_ratios; i++)  in ad7606_oversampling_ratio_avail()
993 		len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", vals[i]);  in ad7606_oversampling_ratio_avail()
994 	buf[len - 1] = '\n';  in ad7606_oversampling_ratio_avail()
1032 	struct device *dev = st->dev;  in ad7606_request_gpios()
1034 	st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start",  in ad7606_request_gpios()
1037 	if (IS_ERR(st->gpio_convst))  in ad7606_request_gpios()
1038 		return PTR_ERR(st->gpio_convst);  in ad7606_request_gpios()
1040 	st->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);  in ad7606_request_gpios()
1041 	if (IS_ERR(st->gpio_reset))  in ad7606_request_gpios()
1042 		return PTR_ERR(st->gpio_reset);  in ad7606_request_gpios()
1044 	st->gpio_range = devm_gpiod_get_optional(dev, "adi,range",  in ad7606_request_gpios()
1046 	if (IS_ERR(st->gpio_range))  in ad7606_request_gpios()
1047 		return PTR_ERR(st->gpio_range);  in ad7606_request_gpios()
1049 	st->gpio_standby = devm_gpiod_get_optional(dev, "standby",  in ad7606_request_gpios()
1051 	if (IS_ERR(st->gpio_standby))  in ad7606_request_gpios()
1052 		return PTR_ERR(st->gpio_standby);  in ad7606_request_gpios()
1054 	st->gpio_frstdata = devm_gpiod_get_optional(dev, "adi,first-data",  in ad7606_request_gpios()
1056 	if (IS_ERR(st->gpio_frstdata))  in ad7606_request_gpios()
1057 		return PTR_ERR(st->gpio_frstdata);  in ad7606_request_gpios()
1059 	if (!st->chip_info->oversampling_num)  in ad7606_request_gpios()
1062 	st->gpio_os = devm_gpiod_get_array_optional(dev,  in ad7606_request_gpios()
1063 						    "adi,oversampling-ratio",  in ad7606_request_gpios()
1065 	return PTR_ERR_OR_ZERO(st->gpio_os);  in ad7606_request_gpios()
1081 		if (st->gpio_convst) {  in ad7606_interrupt()
1082 			gpiod_set_value(st->gpio_convst, 0);  in ad7606_interrupt()
1086 				dev_err(st->dev, "PWM set low failed");  in ad7606_interrupt()
1090 		iio_trigger_poll_nested(st->trig);  in ad7606_interrupt()
1092 		complete(&st->completion);  in ad7606_interrupt()
1104 	if (st->trig != trig)  in ad7606_validate_trigger()
1105 		return -EINVAL;  in ad7606_validate_trigger()
1114 	gpiod_set_value(st->gpio_convst, 1);  in ad7606_buffer_postenable()
1123 	gpiod_set_value(st->gpio_convst, 0);  in ad7606_buffer_predisable()
1139 		*vals = st->oversampling_avail;  in ad7606_read_avail()
1140 		*length = st->num_os_ratios;  in ad7606_read_avail()
1146 		if (st->sw_mode_en)  in ad7606_read_avail()
1147 			ch = chan->scan_index;  in ad7606_read_avail()
1149 		ci = &st->chan_info[ch];  in ad7606_read_avail()
1150 		*vals = (int *)ci->scale_avail;  in ad7606_read_avail()
1151 		*length = ci->num_scales * 2;  in ad7606_read_avail()
1156 		*vals = st->chip_info->calib_offset_avail;  in ad7606_read_avail()
1160 		*vals = (const int *)st->chip_info->calib_phase_avail;  in ad7606_read_avail()
1164 	return -EINVAL;  in ad7606_read_avail()
1191 	if (!st->bops->update_scan_mode)  in ad7606_update_scan_mode()
1194 	return st->bops->update_scan_mode(indio_dev, scan_mask);  in ad7606_update_scan_mode()
1256 	readval = st->bops->reg_read(st, addr);  in ad7606_write_mask()
1263 	return st->bops->reg_write(st, addr, readval);  in ad7606_write_mask()
1276 	 * because the order of channels in iio is 0A, 0B, 1A, 1B...  in ad7616_write_scale_sw()
1278 	ch_index = ch >> 1;  in ad7616_write_scale_sw()
1288 	mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11));  in ad7616_write_scale_sw()
1315 	return st->bops->reg_write(st, AD7606_OS_MODE, val);  in ad7606_write_os_sw()
1328 	st->write_scale = ad7616_write_scale_sw;  in ad7616_sw_mode_setup()
1329 	st->write_os = &ad7616_write_os_sw;  in ad7616_sw_mode_setup()
1331 	if (st->bops->sw_mode_config) {  in ad7616_sw_mode_setup()
1332 		ret = st->bops->sw_mode_config(indio_dev);  in ad7616_sw_mode_setup()
1355 	if (st->gpio_os)  in ad7606b_sw_mode_setup()
1356 		gpiod_multi_set_value_cansleep(st->gpio_os, os);  in ad7606b_sw_mode_setup()
1359 	st->oversampling_avail = ad7606b_oversampling_avail;  in ad7606b_sw_mode_setup()
1360 	st->num_os_ratios = ARRAY_SIZE(ad7606b_oversampling_avail);  in ad7606b_sw_mode_setup()
1362 	st->write_scale = ad7606_write_scale_sw;  in ad7606b_sw_mode_setup()
1363 	st->write_os = &ad7606_write_os_sw;  in ad7606b_sw_mode_setup()
1365 	if (!st->bops->sw_mode_config)  in ad7606b_sw_mode_setup()
1368 	return st->bops->sw_mode_config(indio_dev);  in ad7606b_sw_mode_setup()
1376 	for (i = 0; i < st->chip_info->num_adc_channels; i++) {  in ad7606_set_gain_calib()
1377 		ci = &st->chan_info[i];  in ad7606_set_gain_calib()
1378 		ret = st->bops->reg_write(st, AD7606_CALIB_GAIN(i),  in ad7606_set_gain_calib()
1379 					  DIV_ROUND_CLOSEST(ci->r_gain,  in ad7606_set_gain_calib()
1391 	struct device *dev = indio_dev->dev.parent;  in ad7606_probe_channels()
1396 	slow_bus = !(st->bops->iio_backend_config || st->offload_en);  in ad7606_probe_channels()
1397 	indio_dev->num_channels = st->chip_info->num_adc_channels;  in ad7606_probe_channels()
1399 	/* Slow buses also get 1 more channel for soft timestamp */  in ad7606_probe_channels()
1401 		indio_dev->num_channels++;  in ad7606_probe_channels()
1403 	channels = devm_kcalloc(dev, indio_dev->num_channels, sizeof(*channels),  in ad7606_probe_channels()
1406 		return -ENOMEM;  in ad7606_probe_channels()
1408 	for (i = 0; i < st->chip_info->num_adc_channels; i++) {  in ad7606_probe_channels()
1411 		chan->type = IIO_VOLTAGE;  in ad7606_probe_channels()
1412 		chan->indexed = 1;  in ad7606_probe_channels()
1413 		chan->channel = i;  in ad7606_probe_channels()
1414 		chan->scan_index = i;  in ad7606_probe_channels()
1415 		chan->scan_type.sign = 's';  in ad7606_probe_channels()
1416 		chan->scan_type.realbits = st->chip_info->bits;  in ad7606_probe_channels()
1418 		 * If in SPI offload mode, storagebits are set based  in ad7606_probe_channels()
1419 		 * on the spi-engine hw implementation.  in ad7606_probe_channels()
1421 		chan->scan_type.storagebits = st->offload_en ?  in ad7606_probe_channels()
1422 			st->chip_info->offload_storagebits :  in ad7606_probe_channels()
1423 			(st->chip_info->bits > 16 ? 32 : 16);  in ad7606_probe_channels()
1425 		chan->scan_type.endianness = IIO_CPU;  in ad7606_probe_channels()
1427 		if (indio_dev->modes & INDIO_DIRECT_MODE)  in ad7606_probe_channels()
1428 			chan->info_mask_separate |= BIT(IIO_CHAN_INFO_RAW);  in ad7606_probe_channels()
1430 		if (st->sw_mode_en) {  in ad7606_probe_channels()
1431 			chan->info_mask_separate |= BIT(IIO_CHAN_INFO_SCALE);  in ad7606_probe_channels()
1432 			chan->info_mask_separate_available |=  in ad7606_probe_channels()
1435 			if (st->chip_info->calib_offset_avail) {  in ad7606_probe_channels()
1436 				chan->info_mask_separate |=  in ad7606_probe_channels()
1439 				chan->info_mask_separate_available |=  in ad7606_probe_channels()
1451 				chan->info_mask_shared_by_type |=  in ad7606_probe_channels()
1454 				chan->info_mask_shared_by_all |=  in ad7606_probe_channels()
1457 			chan->info_mask_shared_by_all_available |=  in ad7606_probe_channels()
1460 			chan->info_mask_shared_by_type |=  in ad7606_probe_channels()
1463 			if (st->chip_info->oversampling_avail)  in ad7606_probe_channels()
1464 				chan->info_mask_shared_by_all |=  in ad7606_probe_channels()
1469 			chan->info_mask_shared_by_all |=  in ad7606_probe_channels()
1472 		ret = st->chip_info->scale_setup_cb(indio_dev, chan);  in ad7606_probe_channels()
1480 	indio_dev->channels = channels;  in ad7606_probe_channels()
1500 		return -ENOMEM;  in ad7606_probe()
1505 	ret = devm_mutex_init(dev, &st->lock);  in ad7606_probe()
1509 	st->dev = dev;  in ad7606_probe()
1510 	st->bops = bops;  in ad7606_probe()
1511 	st->base_address = base_address;  in ad7606_probe()
1512 	st->oversampling = 1;  in ad7606_probe()
1513 	st->sw_mode_en = device_property_read_bool(dev, "adi,sw-mode");  in ad7606_probe()
1515 	if (st->sw_mode_en && !chip_info->sw_setup_cb)  in ad7606_probe()
1516 		return dev_err_probe(dev, -EINVAL,  in ad7606_probe()
1530 	if (ret && ret != -ENODEV)  in ad7606_probe()
1534 	st->chip_info = chip_info;  in ad7606_probe()
1536 	if (st->chip_info->oversampling_num) {  in ad7606_probe()
1537 		st->oversampling_avail = st->chip_info->oversampling_avail;  in ad7606_probe()
1538 		st->num_os_ratios = st->chip_info->oversampling_num;  in ad7606_probe()
1545 	if (st->gpio_os) {  in ad7606_probe()
1546 		if (st->gpio_range)  in ad7606_probe()
1547 			indio_dev->info = &ad7606_info_os_and_range;  in ad7606_probe()
1549 			indio_dev->info = &ad7606_info_os;  in ad7606_probe()
1551 		if (st->gpio_range)  in ad7606_probe()
1552 			indio_dev->info = &ad7606_info_range;  in ad7606_probe()
1554 			indio_dev->info = &ad7606_info_no_os_or_range;  in ad7606_probe()
1557 	/* AXI ADC backend doesn't support single read. */  in ad7606_probe()
1558 	indio_dev->modes = st->bops->iio_backend_config ? 0 : INDIO_DIRECT_MODE;  in ad7606_probe()
1559 	indio_dev->name = chip_info->name;  in ad7606_probe()
1561 	/* Using spi-engine with offload support ? */  in ad7606_probe()
1562 	if (st->bops->offload_config) {  in ad7606_probe()
1563 		ret = st->bops->offload_config(dev, indio_dev);  in ad7606_probe()
1574 		dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n");  in ad7606_probe()
1577 	if (st->chip_info->init_delay_ms) {  in ad7606_probe()
1578 		if (msleep_interruptible(st->chip_info->init_delay_ms))  in ad7606_probe()
1579 			return -ERESTARTSYS;  in ad7606_probe()
1583 	if (!st->gpio_convst || st->offload_en) {  in ad7606_probe()
1584 		st->cnvst_pwm = devm_pwm_get(dev, NULL);  in ad7606_probe()
1585 		if (IS_ERR(st->cnvst_pwm))  in ad7606_probe()
1586 			return PTR_ERR(st->cnvst_pwm);  in ad7606_probe()
1588 		/* The PWM is initialized at 1MHz to have a fast enough GPIO emulation. */  in ad7606_probe()
1589 		ret = ad7606_set_sampling_freq(st, 1 * MEGA);  in ad7606_probe()
1603 					       st->cnvst_pwm);  in ad7606_probe()
1608 	if (st->bops->iio_backend_config) {  in ad7606_probe()
1613 		ret = ad7606_set_sampling_freq(st, chip_info->max_samplerate);  in ad7606_probe()
1617 		ret = st->bops->iio_backend_config(dev, indio_dev);  in ad7606_probe()
1621 		indio_dev->setup_ops = &ad7606_backend_buffer_ops;  in ad7606_probe()
1622 	} else if (!st->offload_en) {  in ad7606_probe()
1624 		if (!st->gpio_convst)  in ad7606_probe()
1625 			return dev_err_probe(dev, -EINVAL,  in ad7606_probe()
1628 		init_completion(&st->completion);  in ad7606_probe()
1629 		st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",  in ad7606_probe()
1630 						  indio_dev->name,  in ad7606_probe()
1632 		if (!st->trig)  in ad7606_probe()
1633 			return -ENOMEM;  in ad7606_probe()
1635 		st->trig->ops = &ad7606_trigger_ops;  in ad7606_probe()
1636 		iio_trigger_set_drvdata(st->trig, indio_dev);  in ad7606_probe()
1637 		ret = devm_iio_trigger_register(dev, st->trig);  in ad7606_probe()
1641 		indio_dev->trig = iio_trigger_get(st->trig);  in ad7606_probe()
1645 						chip_info->name, indio_dev);  in ad7606_probe()
1657 	st->write_scale = ad7606_write_scale_hw;  in ad7606_probe()
1658 	st->write_os = ad7606_write_os_hw;  in ad7606_probe()
1660 	/* Offload needs 1 DOUT line, applying this setting in sw_setup_cb. */  in ad7606_probe()
1661 	if (st->sw_mode_en || st->offload_en) {  in ad7606_probe()
1662 		indio_dev->info = &ad7606_info_sw_mode;  in ad7606_probe()
1663 		st->chip_info->sw_setup_cb(indio_dev);  in ad7606_probe()
1666 	if (st->sw_mode_en && st->chip_info->calib_gain_avail) {  in ad7606_probe()
1683 	if (st->gpio_standby) {  in ad7606_suspend()
1684 		gpiod_set_value(st->gpio_range, 1);  in ad7606_suspend()
1685 		gpiod_set_value(st->gpio_standby, 1);  in ad7606_suspend()
1696 	if (st->gpio_standby) {  in ad7606_resume()
1697 		gpiod_set_value(st->gpio_range, st->chan_info[0].range);  in ad7606_resume()
1698 		gpiod_set_value(st->gpio_standby, 1);  in ad7606_resume()