xref: /linux/Documentation/iio/ad7606.rst (revision 60675d4ca1ef0857e44eba5849b74a3a998d0c0f)
1*1346e256SGuillaume Stols.. SPDX-License-Identifier: GPL-2.0-only
2*1346e256SGuillaume Stols
3*1346e256SGuillaume Stols=============
4*1346e256SGuillaume StolsAD7606 driver
5*1346e256SGuillaume Stols=============
6*1346e256SGuillaume Stols
7*1346e256SGuillaume StolsADC driver for Analog Devices Inc. AD7606 and similar devices. The module name
8*1346e256SGuillaume Stolsis ``ad7606``.
9*1346e256SGuillaume Stols
10*1346e256SGuillaume StolsSupported devices
11*1346e256SGuillaume Stols=================
12*1346e256SGuillaume Stols
13*1346e256SGuillaume StolsThe following chips are supported by this driver:
14*1346e256SGuillaume Stols
15*1346e256SGuillaume Stols* `AD7605 <https://www.analog.com/en/products/ad7605.html>`_
16*1346e256SGuillaume Stols* `AD7606 <https://www.analog.com/en/products/ad7606.html>`_
17*1346e256SGuillaume Stols* `AD7606B <https://www.analog.com/en/products/ad7606b.html>`_
18*1346e256SGuillaume Stols* `AD7616 <https://www.analog.com/en/products/ad7616.html>`_
19*1346e256SGuillaume Stols
20*1346e256SGuillaume StolsSupported features
21*1346e256SGuillaume Stols==================
22*1346e256SGuillaume Stols
23*1346e256SGuillaume StolsSPI wiring modes
24*1346e256SGuillaume Stols----------------
25*1346e256SGuillaume Stols
26*1346e256SGuillaume StolsThese ADCs can output data on several SDO lines (1/2/4/8). The driver
27*1346e256SGuillaume Stolscurrently supports only 1 SDO line.
28*1346e256SGuillaume Stols
29*1346e256SGuillaume StolsParallel wiring mode
30*1346e256SGuillaume Stols--------------------
31*1346e256SGuillaume Stols
32*1346e256SGuillaume StolsThere is also a parallel interface, with 16 lines (that can be reduced to 8 in
33*1346e256SGuillaume Stolsbyte mode). The parallel interface is selected by declaring the device as
34*1346e256SGuillaume Stolsplatform in the device tree (with no io-backends node defined, see below).
35*1346e256SGuillaume Stols
36*1346e256SGuillaume StolsIIO-backend mode
37*1346e256SGuillaume Stols----------------
38*1346e256SGuillaume Stols
39*1346e256SGuillaume StolsThis mode allows to reach the best sample rates, but it requires an external
40*1346e256SGuillaume Stolshardware (eg HDL or APU) to handle the low level communication.
41*1346e256SGuillaume StolsThe backend mode is enabled when through the definition of the "io-backends"
42*1346e256SGuillaume Stolsproperty in the device tree.
43*1346e256SGuillaume Stols
44*1346e256SGuillaume StolsThe reference configuration for the current implementation of IIO-backend mode
45*1346e256SGuillaume Stolsis the HDL reference provided by ADI:
46*1346e256SGuillaume Stolshttps://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl
47*1346e256SGuillaume Stols
48*1346e256SGuillaume StolsThis implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWM
49*1346e256SGuillaume Stolsconnected to the conversion trigger pin.
50*1346e256SGuillaume Stols
51*1346e256SGuillaume Stols.. code-block::
52*1346e256SGuillaume Stols
53*1346e256SGuillaume Stols    +---+                                       +----------------------------
54*1346e256SGuillaume Stols    |   |               +-------+               |AD76xx
55*1346e256SGuillaume Stols    | A |  controls     |       |               |
56*1346e256SGuillaume Stols    | D |-------------->|  PWM  |-------------->| cnvst
57*1346e256SGuillaume Stols    | 7 |               |       |               |
58*1346e256SGuillaume Stols    | 6 |               +-------+               |
59*1346e256SGuillaume Stols    | 0 | controls  +-----------+-----------+   |
60*1346e256SGuillaume Stols    | 6 |---------->|           |           |<--| frstdata
61*1346e256SGuillaume Stols    |   |           | Backend   |  Backend  |<--| busy
62*1346e256SGuillaume Stols    | D |           | Driver    |           |   |
63*1346e256SGuillaume Stols    | R |           |           |           |-->| clk
64*1346e256SGuillaume Stols    | I |  requests |+---------+| DMA       |   |
65*1346e256SGuillaume Stols    | V |----------->|  Buffer ||<----      |<=>| DATA
66*1346e256SGuillaume Stols    | E |           |+---------+|           |   |
67*1346e256SGuillaume Stols    | R |           +-----------+-----------+   |
68*1346e256SGuillaume Stols    |   |-------------------------------------->| reset/configuration gpios
69*1346e256SGuillaume Stols    +---+                                       +-----------------------------
70*1346e256SGuillaume Stols
71*1346e256SGuillaume Stols
72*1346e256SGuillaume StolsSoftware and hardware modes
73*1346e256SGuillaume Stols---------------------------
74*1346e256SGuillaume Stols
75*1346e256SGuillaume StolsWhile all the AD7606/AD7616 series parts can be configured using GPIOs, some of
76*1346e256SGuillaume Stolsthem can be configured using register.
77*1346e256SGuillaume Stols
78*1346e256SGuillaume StolsThe chips that support software mode have more values available for configuring
79*1346e256SGuillaume Stolsthe device, as well as more settings, and allow to control the range and
80*1346e256SGuillaume Stolscalibration per channel.
81*1346e256SGuillaume Stols
82*1346e256SGuillaume StolsThe following settings are available per channel in software mode:
83*1346e256SGuillaume Stols - Scale
84*1346e256SGuillaume Stols
85*1346e256SGuillaume StolsAlso, there is a broader choice of oversampling ratios in software mode.
86*1346e256SGuillaume Stols
87*1346e256SGuillaume StolsConversion triggering
88*1346e256SGuillaume Stols---------------------
89*1346e256SGuillaume Stols
90*1346e256SGuillaume StolsThe conversion can be triggered by two distinct ways:
91*1346e256SGuillaume Stols
92*1346e256SGuillaume Stols - A GPIO is connected to the conversion trigger pin, and this GPIO is controlled
93*1346e256SGuillaume Stols   by the driver directly.  In this configuration, the driver sets back the
94*1346e256SGuillaume Stols   conversion trigger pin to high as soon as it has read all the conversions.
95*1346e256SGuillaume Stols
96*1346e256SGuillaume Stols - An external source is connected to the conversion trigger pin. In the
97*1346e256SGuillaume Stols   current implementation, it must be a PWM. In this configuration, the driver
98*1346e256SGuillaume Stols   does not control directly the conversion trigger pin. Instead, it can
99*1346e256SGuillaume Stols   control the PWM's frequency. This trigger is enabled only for iio-backend.
100*1346e256SGuillaume Stols
101*1346e256SGuillaume StolsReference voltage
102*1346e256SGuillaume Stols-----------------
103*1346e256SGuillaume Stols
104*1346e256SGuillaume Stols2 possible reference voltage sources are supported:
105*1346e256SGuillaume Stols
106*1346e256SGuillaume Stols - Internal reference (2.5V)
107*1346e256SGuillaume Stols - External reference (2.5V)
108*1346e256SGuillaume Stols
109*1346e256SGuillaume StolsThe source is determined by the device tree. If ``refin-supply`` is present,
110*1346e256SGuillaume Stolsthen the external reference is used, otherwise the internal reference is used.
111*1346e256SGuillaume Stols
112*1346e256SGuillaume StolsOversampling
113*1346e256SGuillaume Stols------------
114*1346e256SGuillaume Stols
115*1346e256SGuillaume StolsThis family supports oversampling to improve SNR.
116*1346e256SGuillaume StolsIn software mode, the following ratios are available:
117*1346e256SGuillaume Stols1 (oversampling disabled)/2/4/8/16/32/64/128/256.
118*1346e256SGuillaume Stols
119*1346e256SGuillaume StolsUnimplemented features
120*1346e256SGuillaume Stols----------------------
121*1346e256SGuillaume Stols
122*1346e256SGuillaume Stols- 2/4/8 SDO lines
123*1346e256SGuillaume Stols- CRC indication
124*1346e256SGuillaume Stols- Calibration
125*1346e256SGuillaume Stols
126*1346e256SGuillaume StolsDevice buffers
127*1346e256SGuillaume Stols==============
128*1346e256SGuillaume Stols
129*1346e256SGuillaume StolsIIO triggered buffer
130*1346e256SGuillaume Stols--------------------
131*1346e256SGuillaume Stols
132*1346e256SGuillaume StolsThis driver supports IIO triggered buffers, with a "built in" trigger, i.e the
133*1346e256SGuillaume Stolstrigger is allocated and linked by the driver, and a new conversion is triggered
134*1346e256SGuillaume Stolsas soon as the samples are transferred, and a timestamp channel is added to make
135*1346e256SGuillaume Stolsup for the potential jitter induced by the delays in the interrupt handling.
136*1346e256SGuillaume Stols
137*1346e256SGuillaume StolsIIO backend buffer
138*1346e256SGuillaume Stols------------------
139*1346e256SGuillaume Stols
140*1346e256SGuillaume StolsWhen IIO backend is used, the trigger is not needed, and the sample rate is
141*1346e256SGuillaume Stolsconsidered as stable. There is no timestamp channel. The communication is
142*1346e256SGuillaume Stolsdelegated to an external logic, called a backend, and the backend's driver
143*1346e256SGuillaume Stolshandles the buffer. When this mode is enabled, the driver cannot control the
144*1346e256SGuillaume Stolsconversion pin, because the busy pin is bound to the backend.
145