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/linux/arch/x86/kvm/svm/
H A Davic.c42 * use whatever bits remain to assign arbitrary AVIC IDs to VMs. Note, the
86 * Enable / disable AVIC. In "auto" mode (default behavior), AVIC is enabled
89 static int avic = AVIC_AUTO_MODE; variable
90 module_param_cb(avic, &avic_ops, &avic, 0444);
91 __MODULE_PARM_TYPE(avic, "bool");
199 * Note: KVM supports hybrid-AVIC mode, where KVM emulates x2APIC MSR in avic_activate_vmcb()
201 * achieved using AVIC doorbell. KVM disables the APIC access page in avic_activate_vmcb()
203 * AVIC in hybrid mode activates only the doorbell mechanism. in avic_activate_vmcb()
213 * mapping into the TLB while AVIC was disabled. in avic_activate_vmcb()
389 * Inhibit AVIC if the vCPU ID is bigger than what is supported by AVIC in avic_init_backing_page()
[all …]
H A Dsvm.h76 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
77 * AVIC PHYSICAL_TABLE pointer,
78 * AVIC LOGICAL_TABLE pointer
124 /* Struct members for AVIC */
325 * target pCPU), when AVIC is toggled on/off (to (de)activate bypass),
816 /* avic.c */
H A Dsvm.c1502 * The following fields are ignored when AVIC is enabled in svm_set_vintr()
3135 * If not running nested, for AVIC, the only reason to end up here is ExtINTs. in interrupt_window_interception()
3136 * In this case AVIC was temporarily disabled for in interrupt_window_interception()
3139 * If running nested, still remove the VM wide AVIC inhibit to in interrupt_window_interception()
3144 * AVIC still inhibited due to per-cpu AVIC inhibition. in interrupt_window_interception()
3764 * will automatically process AVIC interrupts at the next VMRUN. in svm_complete_interrupt_delivery()
3936 * IRQ window is not needed when AVIC is enabled, in svm_enable_irq_window()
3938 * via AVIC. In such case, KVM needs to temporarily disable AVIC, in svm_enable_irq_window()
3941 * If running nested, AVIC is already locally inhibited in svm_enable_irq_window()
3943 * the VM wide AVIC inhibition. in svm_enable_irq_window()
[all …]
H A Dnested.c1334 * Un-inhibit the AVIC right away, so that other vCPUs can start in nested_svm_vmexit()
/linux/arch/x86/kernel/apic/
H A Dx2apic_savic.c3 * AMD Secure AVIC Support (SEV-SNP Guests)
50 * When Secure AVIC is enabled, RDMSR/WRMSR of the APIC registers
118 pr_err("Error reading unknown Secure AVIC reg offset 0x%x\n", reg); in savic_read()
126 * On WRMSR to APIC_SELF_IPI register by the guest, Secure AVIC hardware
240 pr_err("Error writing unknown Secure AVIC reg offset 0x%x\n", reg); in savic_write()
335 /* Disable Secure AVIC */ in savic_teardown()
347 * Before Secure AVIC is enabled, APIC MSR reads are intercepted. in savic_setup()
356 * present when the vCPU is running in order for Secure AVIC to in savic_setup()
378 pr_err("Secure AVIC enabled in non x2APIC mode\n"); in savic_probe()
392 .name = "secure avic x2apic",
/linux/arch/arm/mach-imx/
H A Davic.c97 * The LPIMR registers use 0 to allow an interrupt, the AVIC in avic_irq_suspend()
130 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, in avic_init_gc()
162 * This function initializes the AVIC hardware and disables all the
186 /* put the AVIC into the reset value with in mxc_init_irq()
203 np = of_find_compatible_node(NULL, NULL, "fsl,avic"); in mxc_init_irq()
236 IRQCHIP_DECLARE(imx_avic, "fsl,avic", imx_avic_init);
H A Dhardware.h49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
57 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
63 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
H A Dmm-imx3.c75 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
116 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
H A Dmx3x.h19 * FC400000 68000000 128M AVIC
98 * ROMP and AVIC
H A DMakefile15 obj-$(CONFIG_MXC_AVIC) += avic.o
/linux/tools/testing/selftests/kvm/x86/
H A Dxapic_state_test.c239 * the guest in order to test AVIC. KVM disallows changing CPUID after in main()
240 * KVM_RUN and AVIC is disabled if _any_ vCPU is allowed to use x2APIC. in main()
246 * AMD's AVIC implementation is buggy (fails to clear the ICR BUSY bit), in main()
252 get_kvm_amd_param_bool("avic"); in main()
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx35.dtsi48 avic: avic-interrupt-controller@68000000 { label
49 compatible = "fsl,imx35-avic", "fsl,avic";
59 interrupt-parent = <&avic>;
H A Dimx31.dtsi44 avic: interrupt-controller@68000000 { label
45 compatible = "fsl,imx31-avic", "fsl,avic";
55 interrupt-parent = <&avic>;
H A Dimx1.dtsi35 compatible = "fsl,imx1-aitc", "fsl,avic";
H A Dimx27.dtsi44 compatible = "fsl,imx27-aitc", "fsl,avic";
H A Dimx25.dtsi57 compatible = "fsl,imx25-asic", "fsl,avic";
/linux/arch/x86/include/asm/
H A Dkvm_host.h1270 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */
1293 * was enabled, to avoid AVIC/APICv bypassing it.
1312 /* INHIBITs that are relevant only to the AMD's AVIC. */
1316 * AVIC is inhibited on a vCPU because it runs a nested guest.
1319 * cannot use the doorbell mechanism to signal interrupts via AVIC when
1326 * which cannot be injected when the AVIC is enabled, thus AVIC
1333 * which AVIC doesn't support for edge triggered interrupts.
1338 * AVIC is disabled because SEV doesn't support it.
1343 * AVIC is disabled because not all vCPUs with a valid LDR have a 1:1
1349 * AVIC is disabled because the vCPU's APIC ID is beyond the max
[all …]
H A Dsev-common.h211 #define GHCB_TERM_SAVIC_FAIL 12 /* Secure AVIC-specific failure */
/linux/include/linux/
H A Damd-iommu.h30 /* IOMMU AVIC Function */
/linux/drivers/irqchip/
H A Dirq-aspeed-vic.c152 .name = "AVIC",
/linux/arch/x86/kvm/
H A Dioapic.c205 * AMD SVM AVIC accelerate EOI write iff the interrupt is edge in ioapic_set_irq()
H A Di8254.c300 * AMD SVM AVIC accelerates EOI write and does not trap. in kvm_pit_set_reinject()
/linux/arch/x86/coco/sev/
H A Dcore.c995 pr_err("Secure AVIC MSR (0x%llx) read returned error (%d)\n", msr, res); in savic_ghcb_msr_read()
1025 pr_err("Secure AVIC MSR (0x%llx) write returned error (%d)\n", msr, res); in savic_ghcb_msr_write()
/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h379 #define X86_FEATURE_AVIC (15*32+13) /* "avic" Virtual Interrupt Controller */
/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv843 0x8000000a, 0, edx, 13, avic , Advanced virtual interrupt controller

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