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/linux/arch/x86/kvm/svm/
H A Davic.c43 * use whatever bits remain to assign arbitrary AVIC IDs to VMs. Note, the
97 * Enable / disable AVIC. In "auto" mode (default behavior), AVIC is enabled
100 static int __ro_after_init avic = AVIC_AUTO_MODE; variable
101 module_param_cb(avic, &avic_ops, &avic, 0444);
102 __MODULE_PARM_TYPE(avic, "bool");
210 * Note: KVM supports hybrid-AVIC mode, where KVM emulates x2APIC MSR in avic_activate_vmcb()
212 * achieved using AVIC doorbell. KVM disables the APIC access page in avic_activate_vmcb()
214 * AVIC in hybrid mode activates only the doorbell mechanism. in avic_activate_vmcb()
224 * mapping into the TLB while AVIC was disabled. in avic_activate_vmcb()
400 * Inhibit AVIC if the vCPU ID is bigger than what is supported by AVIC in avic_init_backing_page()
[all …]
H A Dsvm.h76 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
77 * AVIC PHYSICAL_TABLE pointer,
78 * AVIC LOGICAL_TABLE pointer
126 /* Struct members for AVIC */
345 * target pCPU), when AVIC is toggled on/off (to (de)activate bypass),
882 /* avic.c */
H A Dsvm.c1549 * The following fields are ignored when AVIC is enabled in svm_set_vintr()
3801 * If AVIC was inhibited in order to detect an IRQ window, and there's in svm_inject_irq()
3806 * IRQs, i.e. if KVM is injecting L1 IRQs into L2. AVIC is locally in svm_inject_irq()
3875 * will automatically process AVIC interrupts at the next VMRUN. in svm_complete_interrupt_delivery()
4047 * KVM only enables IRQ windows when AVIC is enabled if there's in svm_enable_irq_window()
4048 * pending ExtINT since it cannot be injected via AVIC (ExtINT in svm_enable_irq_window()
4050 * AVIC is enabled, and so KVM needs to temporarily disable in svm_enable_irq_window()
4051 * AVIC in order to detect when it's ok to inject the ExtINT. in svm_enable_irq_window()
4053 * If running nested, AVIC is already locally inhibited on this in svm_enable_irq_window()
4054 * vCPU (L2 vCPUs use a different MMU that never maps the AVIC in svm_enable_irq_window()
[all …]
H A Dnested.c1415 * Un-inhibit the AVIC right away, so that other vCPUs can start in nested_svm_vmexit()
/linux/arch/x86/kernel/apic/
H A Dx2apic_savic.c3 * AMD Secure AVIC Support (SEV-SNP Guests)
50 * When Secure AVIC is enabled, RDMSR/WRMSR of the APIC registers
118 pr_err("Error reading unknown Secure AVIC reg offset 0x%x\n", reg); in savic_read()
126 * On WRMSR to APIC_SELF_IPI register by the guest, Secure AVIC hardware
240 pr_err("Error writing unknown Secure AVIC reg offset 0x%x\n", reg); in savic_write()
335 /* Disable Secure AVIC */ in savic_teardown()
347 * Before Secure AVIC is enabled, APIC MSR reads are intercepted. in savic_setup()
356 * present when the vCPU is running in order for Secure AVIC to in savic_setup()
378 pr_err("Secure AVIC enabled in non x2APIC mode\n"); in savic_probe()
392 .name = "secure avic x2apic",
/linux/arch/arm/mach-imx/
H A Davic.c97 * The LPIMR registers use 0 to allow an interrupt, the AVIC in avic_irq_suspend()
130 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, in avic_init_gc()
162 * This function initializes the AVIC hardware and disables all the
186 /* put the AVIC into the reset value with in mxc_init_irq()
203 np = of_find_compatible_node(NULL, NULL, "fsl,avic"); in mxc_init_irq()
236 IRQCHIP_DECLARE(imx_avic, "fsl,avic", imx_avic_init);
H A Dhardware.h49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
57 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
63 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
H A Dmm-imx3.c75 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
116 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
H A Dmx3x.h19 * FC400000 68000000 128M AVIC
98 * ROMP and AVIC
H A DMakefile15 obj-$(CONFIG_MXC_AVIC) += avic.o
/linux/tools/testing/selftests/kvm/x86/
H A Dxapic_state_test.c239 * the guest in order to test AVIC. KVM disallows changing CPUID after in main()
240 * KVM_RUN and AVIC is disabled if _any_ vCPU is allowed to use x2APIC. in main()
246 * AMD's AVIC implementation is buggy (fails to clear the ICR BUSY bit), in main()
252 get_kvm_amd_param_bool("avic"); in main()
H A Dxapic_tpr_test.c272 * KVM_RUN and AVIC is disabled if _any_ vCPU is allowed to use x2APIC. in main()
/linux/arch/x86/include/asm/
H A Dkvm_host.h1286 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */
1309 * was enabled, to avoid AVIC/APICv bypassing it.
1328 /* INHIBITs that are relevant only to the AMD's AVIC. */
1332 * AVIC is inhibited on a vCPU because it runs a nested guest.
1335 * cannot use the doorbell mechanism to signal interrupts via AVIC when
1342 * which cannot be injected when the AVIC is enabled, thus AVIC
1349 * which AVIC doesn't support for edge triggered interrupts.
1354 * AVIC is disabled because SEV doesn't support it.
1359 * AVIC is disabled because not all vCPUs with a valid LDR have a 1:1
1365 * AVIC is disabled because the vCPU's APIC ID is beyond the max
[all …]
H A Dsev-common.h211 #define GHCB_TERM_SAVIC_FAIL 12 /* Secure AVIC-specific failure */
/linux/include/linux/
H A Damd-iommu.h30 /* IOMMU AVIC Function */
/linux/drivers/irqchip/
H A Dirq-aspeed-vic.c152 .name = "AVIC",
/linux/arch/x86/
H A DKconfig485 bool "AMD Secure AVIC"
488 Enable this to get AMD Secure AVIC support on guests that have this feature.
490 AMD Secure AVIC provides hardware acceleration for performance sensitive
492 guests. Secure AVIC does not support xAPIC mode. It has functional
/linux/arch/x86/kvm/
H A Dioapic.c205 * AMD SVM AVIC accelerate EOI write iff the interrupt is edge in ioapic_set_irq()
H A Di8254.c300 * AMD SVM AVIC accelerates EOI write and does not trap. in kvm_pit_set_reinject()
H A Dtrace.h1524 * Tracepoint for AMD AVIC
H A Dx86.c10995 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in in kvm_vcpu_update_apicv()
10996 * this case so that KVM can use the AVIC doorbell to inject interrupts in kvm_vcpu_update_apicv()
/linux/arch/x86/coco/sev/
H A Dcore.c995 pr_err("Secure AVIC MSR (0x%llx) read returned error (%d)\n", msr, res); in savic_ghcb_msr_read()
1025 pr_err("Secure AVIC MSR (0x%llx) write returned error (%d)\n", msr, res); in savic_ghcb_msr_write()
/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h379 #define X86_FEATURE_AVIC (15*32+13) /* "avic" Virtual Interrupt Controller */
/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv866 0x8000000a, 0, edx, 13, avic , Advanced virtual interrupt controller
/linux/arch/x86/kvm/mmu/
H A Dmmu.c4711 * using APICv/AVIC to accelerate L2 accesses to L1's APIC, in kvm_mmu_faultin_pfn()
4718 * of breaking APICv/AVIC for L1. in kvm_mmu_faultin_pfn()
4727 * when the AVIC is re-enabled. in kvm_mmu_faultin_pfn()

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