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/linux/arch/x86/kvm/svm/
H A Davic.c43 * use whatever bits remain to assign arbitrary AVIC IDs to VMs. Note, the
97 * Enable / disable AVIC. In "auto" mode (default behavior), AVIC is enabled
100 static int __ro_after_init avic = AVIC_AUTO_MODE; variable
101 module_param_cb(avic, &avic_ops, &avic, 0444);
102 __MODULE_PARM_TYPE(avic, "bool");
187 * Flush the TLB when enabling (x2)AVIC and when transitioning between in avic_activate_vmcb()
199 * instead redirects the access to the AVIC backing page, i.e. to the in avic_activate_vmcb()
216 * Note: KVM supports hybrid-AVIC mode, where KVM emulates x2APIC MSR in avic_activate_vmcb()
218 * achieved using AVIC doorbell. KVM disables the APIC access page in avic_activate_vmcb()
220 * AVIC in hybrid mode activates only the doorbell mechanism. in avic_activate_vmcb()
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H A Dsvm.h80 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
81 * AVIC PHYSICAL_TABLE pointer,
82 * AVIC LOGICAL_TABLE pointer
131 /* Struct members for AVIC */
355 * target pCPU), when AVIC is toggled on/off (to (de)activate bypass),
940 /* avic.c */
H A Dsvm.c1603 * The following fields are ignored when AVIC is enabled in svm_seg()
3983 * If AVIC was inhibited in order to detect an IRQ window, and there's in svm_get_nmi_mask()
3988 * IRQs, i.e. if KVM is injecting L1 IRQs into L2. AVIC is locally in svm_set_nmi_mask()
4057 * will automatically process AVIC interrupts at the next VMRUN. in svm_interrupt_blocked()
4229 * KVM only enables IRQ windows when AVIC is enabled if there's in svm_flush_tlb_all()
4230 * pending ExtINT since it cannot be injected via AVIC (ExtINT in svm_flush_tlb_all()
4232 * AVIC is enabled, and so KVM needs to temporarily disable in svm_flush_tlb_all()
4233 * AVIC in order to detect when it's ok to inject the ExtINT. in svm_flush_tlb_all()
4235 * If running nested, AVIC is already locally inhibited on this in svm_flush_tlb_guest()
4236 * vCPU (L2 vCPUs use a different MMU that never maps the AVIC in svm_flush_tlb_guest()
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H A Dnested.c1470 * Un-inhibit the AVIC right away, so that other vCPUs can start in nested_svm_triple_fault()
H A Dsev.c5042 * 2MB-aligned VMCB, VMSA, PML or AVIC backing page. in sev_handle_rmp_fault()
/linux/arch/x86/kvm/
H A Dx86.h542 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */
565 * was enabled, to avoid AVIC/APICv bypassing it.
584 /* INHIBITs that are relevant only to the AMD's AVIC. */
588 * AVIC is inhibited on a vCPU because it runs a nested guest.
591 * cannot use the doorbell mechanism to signal interrupts via AVIC when
598 * which cannot be injected when the AVIC is enabled, thus AVIC
605 * which AVIC doesn't support for edge triggered interrupts.
610 * AVIC is disabled because SEV doesn't support it.
615 * AVIC i
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H A Di8254.c300 * AMD SVM AVIC accelerates EOI write and does not trap. in kvm_pit_set_reinject()
H A Dtrace.h1524 * Tracepoint for AMD AVIC
H A Dx86.c7940 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in in kvm_set_or_clear_apicv_inhibit()
7941 * this case so that KVM can use the AVIC doorbell to inject interrupts in kvm_set_or_clear_apicv_inhibit()
/linux/arch/arm/mach-imx/
H A Dhardware.h49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
57 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
63 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
H A Dmx3x.h19 * FC400000 68000000 128M AVIC
98 * ROMP and AVIC
H A DMakefile15 obj-$(CONFIG_MXC_AVIC) += avic.o
/linux/tools/testing/selftests/kvm/x86/
H A Dxapic_state_test.c239 * the guest in order to test AVIC. KVM disallows changing CPUID after in main()
240 * KVM_RUN and AVIC is disabled if _any_ vCPU is allowed to use x2APIC. in main()
246 * AMD's AVIC implementation is buggy (fails to clear the ICR BUSY bit), in main()
252 get_kvm_amd_param_bool("avic"); in main()
H A Dxapic_tpr_test.c272 * KVM_RUN and AVIC is disabled if _any_ vCPU is allowed to use x2APIC. in main()
/linux/include/linux/
H A Damd-iommu.h30 /* IOMMU AVIC Function */
/linux/drivers/irqchip/
H A Dirq-aspeed-vic.c152 .name = "AVIC",
/linux/arch/x86/include/asm/
H A Dsev-common.h211 #define GHCB_TERM_SAVIC_FAIL 12 /* Secure AVIC-specific failure */
H A Dcpufeatures.h392 #define X86_FEATURE_AVIC (15*32+13) /* "avic" Virtual Interrupt Controller */
/linux/arch/x86/
H A DKconfig485 bool "AMD Secure AVIC"
488 Enable this to get AMD Secure AVIC support on guests that have this feature.
490 AMD Secure AVIC provides hardware acceleration for performance sensitive
492 guests. Secure AVIC does not support xAPIC mode. It has functional
/linux/arch/x86/coco/sev/
H A Dcore.c991 pr_err("Secure AVIC MSR (0x%llx) read returned error (%d)\n", msr, res); in savic_ghcb_msr_read()
1021 pr_err("Secure AVIC MSR (0x%llx) write returned error (%d)\n", msr, res); in savic_ghcb_msr_write()
/linux/Documentation/devicetree/bindings/
H A Dvendor-prefixes.yaml218 "^avic,.*":
219 description: Shanghai AVIC Optoelectronics Co., Ltd.
/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h379 #define X86_FEATURE_AVIC (15*32+13) /* "avic" Virtual Interrupt Controller */
/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv866 0x8000000a, 0, edx, 13, avic , Advanced virtual interrupt controller
/linux/arch/x86/kvm/mmu/
H A Dmmu.c4794 * using APICv/AVIC to accelerate L2 accesses to L1's APIC, in kvm_mmu_faultin_pfn()
4801 * of breaking APICv/AVIC for L1. in kvm_mmu_faultin_pfn()
4810 * when the AVIC is re-enabled. in kvm_mmu_faultin_pfn()
/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt473 This mode requires kvm-amd.avic=1.