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/linux/drivers/pci/controller/dwc/
H A Dpcie-designware-host.c422 struct dw_pcie_ob_atu_cfg atu = {0}; in dw_pcie_config_ecam_iatu() local
435 atu.index = 0; in dw_pcie_config_ecam_iatu()
436 atu.type = PCIE_ATU_TYPE_CFG0; in dw_pcie_config_ecam_iatu()
437 atu.parent_bus_addr = pp->cfg0_base + SZ_1M; in dw_pcie_config_ecam_iatu()
439 atu.size = SZ_1M; in dw_pcie_config_ecam_iatu()
440 atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; in dw_pcie_config_ecam_iatu()
441 ret = dw_pcie_prog_outbound_atu(pci, &atu); in dw_pcie_config_ecam_iatu()
451 atu.index = 1; in dw_pcie_config_ecam_iatu()
452 atu.type = PCIE_ATU_TYPE_CFG1; in dw_pcie_config_ecam_iatu()
453 atu.parent_bus_addr = pp->cfg0_base + SZ_2M; in dw_pcie_config_ecam_iatu()
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H A Dpcie-designware.c142 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); in dw_pcie_get_resources()
397 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
417 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
435 * bit in the Control register-1 of the ATU outbound region acts in dw_pcie_enable_ecrc()
443 * registers, the transactions going through ATU won't have TLP in dw_pcie_enable_ecrc()
473 const struct dw_pcie_ob_atu_cfg *atu) in dw_pcie_prog_outbound_atu() argument
475 u64 parent_bus_addr = atu->parent_bus_addr; in dw_pcie_prog_outbound_atu()
479 limit_addr = parent_bus_addr + atu->size - 1; in dw_pcie_prog_outbound_atu()
483 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { in dw_pcie_prog_outbound_atu()
487 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, in dw_pcie_prog_outbound_atu()
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H A Dpcie-designware-ep.c178 struct dw_pcie_ob_atu_cfg *atu) in dw_pcie_ep_outbound_atu() argument
190 atu->index = free_win; in dw_pcie_ep_outbound_atu()
191 ret = dw_pcie_prog_outbound_atu(pci, atu); in dw_pcie_ep_outbound_atu()
196 ep->outbound_addr[free_win] = atu->parent_bus_addr; in dw_pcie_ep_outbound_atu()
475 struct dw_pcie_ob_atu_cfg atu = { 0 }; in dw_pcie_ep_map_addr() local
477 atu.func_no = func_no; in dw_pcie_ep_map_addr()
478 atu.type = PCIE_ATU_TYPE_MEM; in dw_pcie_ep_map_addr()
479 atu.parent_bus_addr = addr - pci->parent_bus_offset; in dw_pcie_ep_map_addr()
480 atu.pci_addr = pci_addr; in dw_pcie_ep_map_addr()
481 atu.size = size; in dw_pcie_ep_map_addr()
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/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal1_atu.c3 * Marvell 88E6xxx Address Translation Unit (ATU) support
18 /* Offset 0x01: ATU FID Register */
25 /* Offset 0x0A: ATU Control Register */
110 /* Offset 0x0B: ATU Operation Register */
144 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_op()
156 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_op()
160 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_op()
192 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_fid_read()
200 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_fid_read()
204 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_fid_read()
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H A Dglobal1.h44 /* Offset 0x01: ATU FID Register */
112 /* Offset 0x0A: ATU Control Register */
117 /* Offset 0x0B: ATU Operation Register */
134 /* Offset 0x0C: ATU Data Register */
166 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
167 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
168 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
H A Ddevlink.c112 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); in mv88e6xxx_devlink_atu_bin_get()
118 dev_err(chip->dev, "failed to perform ATU get next\n"); in mv88e6xxx_devlink_atu_bin_get()
124 dev_err(chip->dev, "failed to get ATU stats\n"); in mv88e6xxx_devlink_atu_bin_get()
187 err = dsa_devlink_resource_register(ds, "ATU", in mv88e6xxx_setup_devlink_resources()
304 /* The ATU entry varies between mv88e6xxx chipset generations. Define
664 .name = "atu",
/linux/arch/sparc/include/asm/
H A Diommu_64.h30 /* Data structures for SPARC ATU architecture */
46 struct atu { struct
57 struct atu *atu; argument
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sm8350.yaml31 - const: atu # ATU address space
99 reg-names = "parf", "dbi", "elbi", "atu", "config";
H A Dqcom,pcie-sc8180x.yaml31 - const: atu # ATU address space
97 "atu",
H A Dqcom,pcie-sm8150.yaml36 - const: atu # ATU address space
100 reg-names = "parf", "dbi", "elbi", "atu", "config";
H A Dqcom,pcie-sc8280xp.yaml33 - const: atu # ATU address space
113 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
H A Dqcom,pcie-sa8775p.yaml35 - const: atu # ATU address space
107 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
H A Dqcom,pcie-x1e80100.yaml30 - const: atu # ATU address space
100 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
H A Dintel,keembay-pcie-ep.yaml24 - const: atu
62 reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
H A Dqcom,pcie-sm8250.yaml31 - const: atu # ATU address space
110 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
H A Dqcom,pcie-sc7280.yaml31 - const: atu # ATU address space
102 reg-names = "parf", "dbi", "elbi", "atu", "config";
H A Dqcom,pcie-sm8550.yaml38 - const: atu # ATU address space
109 reg-names = "parf", "dbi", "elbi", "atu", "config";
H A Dti,am65-pci-ep.yaml29 - const: atu
70 reg-names = "app", "dbics", "addr_space", "atu";
H A Dst,stm32-pcie-ep.yaml34 - const: atu
63 reg-names = "dbi", "dbi2", "atu", "addr_space";
H A Dhost-generic-pci.yaml68 DesignWare PCIe controller in RC mode with static ATU window mappings
72 is there any reason for the driver to reconfigure ATU windows for
75 In cases where the IP was synthesized with a minimum ATU window size
H A Dintel,keembay-pcie.yaml32 - const: atu
83 reg-names = "dbi", "atu", "config", "apb";
H A Drcar-gen4-pci-ep.yaml32 - const: atu
104 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
H A Dsophgo,sg2044-pcie.yaml35 - const: atu
98 reg-names = "dbi", "atu", "config", "app";
H A Drockchip-dw-pcie-ep.yaml41 - const: atu
68 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
H A Drcar-gen4-pci-host.yaml32 - const: atu
102 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";

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