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/linux/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2500-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED AST2500 Pin Controller
10 - Andrew Jeffery <andrew@aj.id.au>
16 - compatible: Should be one of the following:
17 "aspeed,ast2500-scu", "syscon", "simple-mfd"
18 "aspeed,g5-scu", "syscon", "simple-mfd"
25 const: aspeed,ast2500-pinctrl
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Daspeed,ast2xxx-scu-ic.txt1 Aspeed AST25XX and AST26XX SCU Interrupt Controller
4 - #interrupt-cells : must be 1
5 - compatible : must be "aspeed,ast2500-scu-ic",
6 "aspeed,ast2600-scu-ic0" or
7 "aspeed,ast2600-scu-ic1"
8 - interrupts : interrupt from the parent controller
9 - interrupt-controller : indicates that the controller receives and
17 scu_ic: interrupt-controller@18 {
18 #interrupt-cells = <1>;
19 compatible = "aspeed,ast2500-scu-ic";
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/linux/Documentation/devicetree/bindings/misc/
H A Daspeed-p2a-ctrl.txt2 Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
14 - compatible: must be one of:
15 - "aspeed,ast2400-p2a-ctrl"
16 - "aspeed,ast2500-p2a-ctrl"
21 - reg: A hint for the memory regions associated with the P2A controller
22 - memory-region: A phandle to a reserved_memory region to be used for the PCI
25 The p2a-control node should be the child of a syscon node with the required
28 - compatible : Should be one of the following:
29 "aspeed,ast2400-scu", "syscon", "simple-mfd"
30 "aspeed,ast2500-scu", "syscon", "simple-mfd"
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/linux/drivers/gpu/drm/aspeed/
H A Daspeed_gfx_drv.c1 // SPDX-License-Identifier: GPL-2.0+
5 #include <linux/dma-mapping.h>
37 * The AST2500 supports a total of 3 output paths:
56 * The driver was written with the 'AST2500 Software Programming Guide' v17,
61 u32 dac_reg; /* DAC register in SCU */
63 u32 vga_scratch_reg; /* VGA scratch register in SCU */
93 { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
94 { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
95 { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
114 drm->mode_config.min_width = 0; in aspeed_gfx_setup_mode_config()
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/linux/Documentation/devicetree/bindings/spi/
H A Daspeed,ast2600-fmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
11 - Cédric Le Goater <clg@kaod.org>
15 SPI) of the AST2400, AST2500 and AST2600 SOCs.
18 - $ref: spi-controller.yaml#
23 - aspeed,ast2600-fmc
24 - aspeed,ast2600-spi
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/linux/drivers/soc/aspeed/
H A Daspeed-lpc-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
40 struct regmap *scu; member
45 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
52 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
53 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
55 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
56 return -EINVAL; in aspeed_lpc_ctrl_mmap()
61 if (remap_pfn_range(vma, vma->vm_start, in aspeed_lpc_ctrl_mmap()
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/linux/drivers/fsi/
H A Dfsi-master-ast-cf.c1 // SPDX-License-Identifier: GPL-2.0+
25 #include "fsi-master.h"
26 #include "cf-fsi-fw.h"
28 #define FW_FILE_NAME "cf-fsi-fw.bin"
30 /* Common SCU based coprocessor control registers */
35 /* AST2500 specific ones */
90 struct regmap *scu; member
132 msg->msg <<= bits; in msg_push_bits()
133 msg->msg |= data & ((1ull << bits) - 1); in msg_push_bits()
134 msg->bits += bits; in msg_push_bits()
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/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
7 compatible = "aspeed,ast2500";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
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H A Daspeed-g6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "aspeed,ast2600-smp";
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/linux/drivers/irqchip/
H A Dirq-aspeed-scu-ic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller
42 struct regmap *scu; member
55 unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT; in aspeed_scu_ic_irq_handler()
60 * The SCU IC has just one register to control its operation and read in aspeed_scu_ic_irq_handler()
69 regmap_read(scu_ic->scu, scu_ic->reg, &sts); in aspeed_scu_ic_irq_handler()
70 enabled = sts & scu_ic->irq_enable; in aspeed_scu_ic_irq_handler()
73 bit = scu_ic->irq_shift; in aspeed_scu_ic_irq_handler()
74 max = scu_ic->num_irqs + bit; in aspeed_scu_ic_irq_handler()
77 generic_handle_domain_irq(scu_ic->irq_domain, in aspeed_scu_ic_irq_handler()
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/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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/linux/drivers/gpu/drm/ast/
H A Dast_drv.c14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
43 static int ast_modeset = -1;
139 struct device *dev = &pdev->dev; in ast_detect_chip()
140 struct device_node *np = dev->of_node; in ast_detect_chip()
148 * Find configuration mode and read SCU revision in ast_detect_chip()
151 /* Check if we have device-tree properties */ in ast_detect_chip()
152 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) { in ast_detect_chip()
156 } else if (pdev->device == PCI_CHIP_AST2000) { // Not all families have a P2A bridge in ast_detect_chip()
158 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge in ast_detect_chip()
170 /* Patch AST2500/AST2510 */ in ast_detect_chip()
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/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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/linux/drivers/iio/adc/
H A Daspeed_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Ast2400/Ast2500:
16 #include <linux/clk-provider.h>
178 struct regmap *scu; in aspeed_adc_set_trim_data() local
184 dev_warn(data->dev, "Couldn't find syscon node\n"); in aspeed_adc_set_trim_data()
185 return -EOPNOTSUPP; in aspeed_adc_set_trim_data()
187 scu = syscon_node_to_regmap(syscon); in aspeed_adc_set_trim_data()
189 if (IS_ERR(scu)) { in aspeed_adc_set_trim_data()
190 dev_warn(data->dev, "Failed to get syscon regmap\n"); in aspeed_adc_set_trim_data()
191 return -EOPNOTSUPP; in aspeed_adc_set_trim_data()
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/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
12 #include <linux/dma-mapping.h>
54 /* For NC-SI to register a fixed-link phy device */
102 /* AST2500/AST2600 RMII ref clock gate */
126 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
130 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
132 priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
136 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
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/linux/drivers/pinctrl/aspeed/
H A Dpinmux-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * read-only).
23 * SoC Multi-function Pin Expression Examples
24 * ------------------------------------------
26 * Here are some sample mux configurations from the AST2400 and AST2500
34 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
36 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
38 * C5 is a multi-signal pin (high and low priority signals). Here we touch
41 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
43 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
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H A Dpinctrl-aspeed-g5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/pinctrl/pinconf-generic.h>
21 #include "../pinctrl-utils.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
37 * reset control and MAC clock configuration registers. The AST2500 goes a step
45 #define SCU80 0x80 /* Multi-function Pin Control #1 */
46 #define SCU84 0x84 /* Multi-function Pin Control #2 */
47 #define SCU88 0x88 /* Multi-function Pin Control #3 */
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