1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller
42 	struct regmap *scu;  member
55 	unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT;  in aspeed_scu_ic_irq_handler()
60 	 * The SCU IC has just one register to control its operation and read  in aspeed_scu_ic_irq_handler()
69 	regmap_read(scu_ic->scu, scu_ic->reg, &sts);  in aspeed_scu_ic_irq_handler()
70 	enabled = sts & scu_ic->irq_enable;  in aspeed_scu_ic_irq_handler()
73 	bit = scu_ic->irq_shift;  in aspeed_scu_ic_irq_handler()
74 	max = scu_ic->num_irqs + bit;  in aspeed_scu_ic_irq_handler()
77 		generic_handle_domain_irq(scu_ic->irq_domain,  in aspeed_scu_ic_irq_handler()
78 					  bit - scu_ic->irq_shift);  in aspeed_scu_ic_irq_handler()
80 		regmap_write_bits(scu_ic->scu, scu_ic->reg, mask,  in aspeed_scu_ic_irq_handler()
90 	unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) |  in aspeed_scu_ic_irq_mask()
91 		(scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);  in aspeed_scu_ic_irq_mask()
98 	regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0);  in aspeed_scu_ic_irq_mask()
104 	unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);  in aspeed_scu_ic_irq_unmask()
106 		(scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);  in aspeed_scu_ic_irq_unmask()
113 	regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit);  in aspeed_scu_ic_irq_unmask()
120 	return -EINVAL;  in aspeed_scu_ic_irq_set_affinity()
124 	.name			= "aspeed-scu-ic",
134 	irq_set_chip_data(irq, domain->host_data);  in aspeed_scu_ic_map()
149 	if (!node->parent) {  in aspeed_scu_ic_of_init_common()
150 		rc = -ENODEV;  in aspeed_scu_ic_of_init_common()
154 	scu_ic->scu = syscon_node_to_regmap(node->parent);  in aspeed_scu_ic_of_init_common()
155 	if (IS_ERR(scu_ic->scu)) {  in aspeed_scu_ic_of_init_common()
156 		rc = PTR_ERR(scu_ic->scu);  in aspeed_scu_ic_of_init_common()
159 	regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_STATUS, ASPEED_SCU_IC_STATUS);  in aspeed_scu_ic_of_init_common()
160 	regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_ENABLE, 0);  in aspeed_scu_ic_of_init_common()
164 		rc = -EINVAL;  in aspeed_scu_ic_of_init_common()
168 	scu_ic->irq_domain = irq_domain_add_linear(node, scu_ic->num_irqs,  in aspeed_scu_ic_of_init_common()
171 	if (!scu_ic->irq_domain) {  in aspeed_scu_ic_of_init_common()
172 		rc = -ENOMEM;  in aspeed_scu_ic_of_init_common()
193 		return -ENOMEM;  in aspeed_scu_ic_of_init()
195 	scu_ic->irq_enable = ASPEED_SCU_IC_ENABLE;  in aspeed_scu_ic_of_init()
196 	scu_ic->irq_shift = ASPEED_SCU_IC_SHIFT;  in aspeed_scu_ic_of_init()
197 	scu_ic->num_irqs = ASPEED_SCU_IC_NUM_IRQS;  in aspeed_scu_ic_of_init()
198 	scu_ic->reg = ASPEED_SCU_IC_REG;  in aspeed_scu_ic_of_init()
209 		return -ENOMEM;  in aspeed_ast2600_scu_ic0_of_init()
211 	scu_ic->irq_enable = ASPEED_AST2600_SCU_IC0_ENABLE;  in aspeed_ast2600_scu_ic0_of_init()
212 	scu_ic->irq_shift = ASPEED_AST2600_SCU_IC0_SHIFT;  in aspeed_ast2600_scu_ic0_of_init()
213 	scu_ic->num_irqs = ASPEED_AST2600_SCU_IC0_NUM_IRQS;  in aspeed_ast2600_scu_ic0_of_init()
214 	scu_ic->reg = ASPEED_AST2600_SCU_IC0_REG;  in aspeed_ast2600_scu_ic0_of_init()
225 		return -ENOMEM;  in aspeed_ast2600_scu_ic1_of_init()
227 	scu_ic->irq_enable = ASPEED_AST2600_SCU_IC1_ENABLE;  in aspeed_ast2600_scu_ic1_of_init()
228 	scu_ic->irq_shift = ASPEED_AST2600_SCU_IC1_SHIFT;  in aspeed_ast2600_scu_ic1_of_init()
229 	scu_ic->num_irqs = ASPEED_AST2600_SCU_IC1_NUM_IRQS;  in aspeed_ast2600_scu_ic1_of_init()
230 	scu_ic->reg = ASPEED_AST2600_SCU_IC1_REG;  in aspeed_ast2600_scu_ic1_of_init()
235 IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init);
236 IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init);
237 IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0",
239 IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1",