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/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
[all …]
H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra-audio-graph-card.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com>
19 - $ref: audio-graph.yaml#
24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card
27 clocks:
[all …]
H A Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-ahub
[all …]
H A Dnvidia,tegra210-dmic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
24 pattern: "^dmic@[0-9a-f]*$"
28 - const: nvidia,tegra210-dmic
29 - items:
[all …]
H A Dnvidia,tegra186-dspk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Density Modulation (PDM) transmitter that up-samples the input to
13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
21 - $ref: dai-common.yaml#
25 pattern: "^dspk@[0-9a-f]*$"
[all …]
H A Dnvidia,tegra210-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Inter-IC Sound (I2S) controller implements full-duplex,
11 bi-directional and single direction point-to-point serial
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
24 pattern: "^i2s@[0-9a-f]*$"
[all …]
H A Dbrcm,cygnus-audio.txt4 - compatible : "brcm,cygnus-audio"
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
[all …]
H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
H A Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
[all …]
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-j722s-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
21 compatible = "ti,am64-wiz-10g";
23 #address-cells = <1>;
[all …]
/linux/drivers/clk/
H A Dclk-conf.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
9 #include <linux/clk/clk-conf.h>
21 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
22 "#clock-cells"); in __set_clk_parents()
23 if (num_parents == -EINVAL) in __set_clk_parents()
24 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
28 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
29 "#clock-cells", index, &clkspec); in __set_clk_parents()
32 if (rc == -ENOENT) in __set_clk_parents()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
[all …]
H A Dimx8mm-overdrive.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
7 assigned-clock-rates = <0>, <1000000000>;
11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
14 assigned-clock-rates = <0>, <1000000000>;
18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
25 assigned-clock-rates = <750000000>,
H A Dimx8mn-evk.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/usb/pd.h>
11 stdout-path = &uart2;
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
22 default-state = "on";
26 hdmi-connector {
27 compatible = "hdmi-connector";
[all …]
H A Dimx8mm-beacon-baseboard.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
12 num-channels = <1>;
13 #sound-dai-cells = <0>;
17 compatible = "gpio-leds";
22 default-state = "off";
28 default-state = "off";
34 default-state = "off";
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,vcodec-encoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 - items:
21 - enum:
22 - mediatek,mt8173-vcodec-enc-vp8
23 - mediatek,mt8173-vcodec-enc
24 - mediatek,mt8183-vcodec-enc
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dti,j721e-ufs.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
15 - const: ti,j721e-ufs
21 clocks:
23 description: phandle to the M-PHY clock
25 power-domains:
28 assigned-clocks:
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dst,stm32-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
18 - st,stm32mp25-rtc
23 clocks:
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroid-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
22 stdout-path = &serial_1;
26 compatible = "samsung,secure-firmware";
[all …]

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