Searched +full:artpec8 +full:- +full:cmu +full:- +full:fsys (Results 1 – 2 of 2) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | axis,artpec8-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Axis ARTPEC-8 SoC clock controller
10 - Jesper Nilsson <jesper.nilsson@axis.com>
13 ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
14 units, generating clocks for different domains. Those CMU units are modeled
17 This external clock must be defined as a fixed-rate clock in dts.
19 CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
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| /linux/drivers/clk/samsung/ |
| H A D | clk-artpec8.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Common Clock Framework support for ARTPEC-8 SoC.
11 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/axis,artpec8-clk.h>
16 #include "clk-exynos-arm64.h"
842 CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init);
992 * artpec8_cmu_probe - Probe function for ARTPEC platform clocks
1000 struct device *dev = &pdev->dev; in artpec8_cmu_probe()
1003 exynos_arm64_register_cmu(dev, dev->of_node, info); in artpec8_cmu_probe()
1010 .compatible = "axis,artpec8-cmu-cmu",
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