Lines Matching +full:artpec8 +full:- +full:cmu +full:- +full:fsys
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Axis ARTPEC-8 SoC clock controller
10 - Jesper Nilsson <jesper.nilsson@axis.com>
13 ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
14 units, generating clocks for different domains. Those CMU units are modeled
17 This external clock must be defined as a fixed-rate clock in dts.
19 CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
26 'include/dt-bindings/clock/axis,artpec8-clk.h' header.
31 - axis,artpec8-cmu-cmu
32 - axis,artpec8-cmu-bus
33 - axis,artpec8-cmu-core
34 - axis,artpec8-cmu-cpucl
35 - axis,artpec8-cmu-fsys
36 - axis,artpec8-cmu-imem
37 - axis,artpec8-cmu-peri
46 clock-names:
50 "#clock-cells":
54 - compatible
55 - reg
56 - clocks
57 - clock-names
58 - "#clock-cells"
61 - if:
64 const: axis,artpec8-cmu-cmu
70 - description: External reference clock (25 MHz)
72 clock-names:
74 - const: fin_pll
76 - if:
79 const: axis,artpec8-cmu-bus
85 - description: External reference clock (25 MHz)
86 - description: CMU_BUS BUS clock (from CMU_CMU)
87 - description: CMU_BUS DLP clock (from CMU_CMU)
89 clock-names:
91 - const: fin_pll
92 - const: bus
93 - const: dlp
95 - if:
98 const: axis,artpec8-cmu-core
104 - description: External reference clock (25 MHz)
105 - description: CMU_CORE main clock (from CMU_CMU)
106 - description: CMU_CORE DLP clock (from CMU_CMU)
108 clock-names:
110 - const: fin_pll
111 - const: main
112 - const: dlp
114 - if:
117 const: axis,artpec8-cmu-cpucl
123 - description: External reference clock (25 MHz)
124 - description: CMU_CPUCL switch clock (from CMU_CMU)
126 clock-names:
128 - const: fin_pll
129 - const: switch
131 - if:
134 const: axis,artpec8-cmu-fsys
140 - description: External reference clock (25 MHz)
141 - description: CMU_FSYS SCAN0 clock (from CMU_CMU)
142 - description: CMU_FSYS SCAN1 clock (from CMU_CMU)
143 - description: CMU_FSYS BUS clock (from CMU_CMU)
144 - description: CMU_FSYS IP clock (from CMU_CMU)
146 clock-names:
148 - const: fin_pll
149 - const: scan0
150 - const: scan1
151 - const: bus
152 - const: ip
154 - if:
157 const: axis,artpec8-cmu-imem
163 - description: External reference clock (25 MHz)
164 - description: CMU_IMEM ACLK clock (from CMU_CMU)
165 - description: CMU_IMEM JPEG clock (from CMU_CMU)
167 clock-names:
169 - const: fin_pll
170 - const: aclk
171 - const: jpeg
173 - if:
176 const: axis,artpec8-cmu-peri
182 - description: External reference clock (25 MHz)
183 - description: CMU_PERI IP clock (from CMU_CMU)
184 - description: CMU_PERI AUDIO clock (from CMU_CMU)
185 - description: CMU_PERI DISP clock (from CMU_CMU)
187 clock-names:
189 - const: fin_pll
190 - const: ip
191 - const: audio
192 - const: disp
198 - |
199 #include <dt-bindings/clock/axis,artpec8-clk.h>
201 cmu_fsys: clock-controller@16c10000 {
202 compatible = "axis,artpec8-cmu-fsys";
204 #clock-cells = <1>;
210 clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";