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/linux/Documentation/devicetree/bindings/regulator/
H A Danatop-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Anatop Voltage Regulators
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
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/linux/drivers/regulator/
H A Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
86 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
92 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
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/linux/arch/arm/mach-imx/
H A Danatop.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
35 static struct regmap *anatop; variable
37 static void imx_anatop_enable_weak2p5(bool enable) in imx_anatop_enable_weak2p5() argument
41 regmap_read(anatop, ANADIG_ANA_MISC0, &val); in imx_anatop_enable_weak2p5()
45 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? in imx_anatop_enable_weak2p5()
47 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); in imx_anatop_enable_weak2p5()
50 static void imx_anatop_enable_fet_odrive(bool enable) in imx_anatop_enable_fet_odrive() argument
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
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H A Dmach-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
45 * as they are used for slots1-7 PERST#
54 if (dev->devfn != 0) in ventana_pciesw_early_fixup()
58 dw |= 0xaaa8; // GPIO1-7 outputs in ventana_pciesw_early_fixup()
62 dw |= 0xfe; // GPIO1-7 output high in ventana_pciesw_early_fixup()
87 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); in imx6q_1588_init()
95 * clk-imx6q.c will do needed configuration. in imx6q_1588_init()
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/drivers/clk/imx/
H A Dclk-imx6sl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
14 #include <dt-bindings/clock/imx6sl-clock.h>
19 #define BM_CCSR_PLL1_SW_CLK_SEL BIT(2)
22 #define BM_CDHIPR_ARM_PODF_BUSY BIT(16)
29 #define BM_PLL_ARM_POWERDOWN BIT(12)
30 #define BM_PLL_ARM_ENABLE BIT(13)
31 #define BM_PLL_ARM_LOCK BIT(31)
123 * 396MHz -> 132MHz;
124 * 792MHz -> 158.4MHz;
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H A Dclk-vf610.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
10 #include <dt-bindings/clock/vf610-clock.h>
199 np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); in vf610_clocks_init()
252 clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10)); in vf610_clocks_init()
347 * selectable clock sources, both use a common enable bit in vf610_clocks_init()
349 * "ftm0_ext_fix" make it serve only for enable/disable. in vf610_clocks_init()
440 clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7)); in vf610_clocks_init()
472 CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
H A Dclk-imx6sll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2017-2018 NXP.
7 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <linux/clk-provider.h>
89 clk_hw_data->num = IMX6SLL_CLK_END; in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
101 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop"); in imx6sll_clocks_init()
148 * Bit 20 is the reserved and read-only bit, we do this only for: in imx6sll_clocks_init()
149 * - Do nothing for usbphy clk_enable/disable in imx6sll_clocks_init()
150 * - Keep refcount when do usbphy clk_enable/disable, in that case, in imx6sll_clocks_init()
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H A Dclk-imx6sx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <linux/clk-provider.h>
131 clk_hw_data->num = IMX6SX_CLK_CLK_END; in imx6sx_clocks_init()
132 hws = clk_hw_data->hws; in imx6sx_clocks_init()
147 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
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H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
154 return -ENOENT; in ldb_di_sel_by_clock_id()
165 return -ENOENT; in ldb_di_sel_by_clock_id()
177 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
178 "#clock-cells"); in of_assigned_ldb_sels()
180 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
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H A Dclk-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
138 clk_hw_data->num = IMX6UL_CLK_END; in imx6ul_clocks_init()
139 hws = clk_hw_data->hws; in imx6ul_clocks_init()
150 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); in imx6ul_clocks_init()
180 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
181 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
182 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
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