Lines Matching +full:anatop +full:- +full:enable +full:- +full:bit

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44  * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
45  * as they are used for slots1-7 PERST#
54 	if (dev->devfn != 0)  in ventana_pciesw_early_fixup()
58 	dw |= 0xaaa8; // GPIO1-7 outputs  in ventana_pciesw_early_fixup()
62 	dw |= 0xfe;   // GPIO1-7 output high  in ventana_pciesw_early_fixup()
87 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");  in imx6q_1588_init()
95 	 * clk-imx6q.c will do needed configuration.  in imx6q_1588_init()
114 	 * If enet_ref from ANATOP/CCM is the PTP clock source, we need to  in imx6q_1588_init()
115 	 * set bit IOMUXC_GPR1[21].  Or the PTP clock must be from pad  in imx6q_1588_init()
116 	 * (external OSC), and we need to clear the bit.  in imx6q_1588_init()
121 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");  in imx6q_1588_init()
127 		pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n");  in imx6q_1588_init()
141 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");  in imx6q_axi_init()
144 		 * Enable the cacheable attribute of VPU and IPU  in imx6q_axi_init()
165 		pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");  in imx6q_axi_init()
174 		 * Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0),  in imx6q_init_machine()
177 		imx_print_silicon_rev("i.MX6QP", imx_get_soc_revision() - 0x10);  in imx6q_init_machine()
205 		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);  in imx6q_init_late()
221 	imx6_pm_ccm_init("fsl,imx6q-ccm");  in imx6q_init_irq()