Lines Matching +full:anatop +full:- +full:enable +full:- +full:bit

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright 2013-2014 Freescale Semiconductor, Inc.
14 #include <dt-bindings/clock/imx6sl-clock.h>
19 #define BM_CCSR_PLL1_SW_CLK_SEL	BIT(2)
22 #define BM_CDHIPR_ARM_PODF_BUSY	BIT(16)
29 #define BM_PLL_ARM_POWERDOWN	BIT(12)
30 #define BM_PLL_ARM_ENABLE	BIT(13)
31 #define BM_PLL_ARM_LOCK		BIT(31)
123  * 396MHz   ->   132MHz;
124  * 792MHz   ->   158.4MHz;
125  * 996MHz   ->   142.3MHz;
140 static void imx6sl_enable_pll_arm(bool enable)  in imx6sl_enable_pll_arm()  argument
145 	if (enable) {  in imx6sl_enable_pll_arm()
193 	clk_hw_data->num = IMX6SL_CLK_END;  in imx6sl_clocks_init()
194 	hws = clk_hw_data->hws;  in imx6sl_clocks_init()
202 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");  in imx6sl_clocks_init()
234 	clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk);  in imx6sl_clocks_init()
235 	clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk);  in imx6sl_clocks_init()
236 	clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk);  in imx6sl_clocks_init()
237 	clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk);  in imx6sl_clocks_init()
238 	clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk);  in imx6sl_clocks_init()
239 	clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk);  in imx6sl_clocks_init()
240 	clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk);  in imx6sl_clocks_init()
251 …SL_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));  in imx6sl_clocks_init()
252 …hws[IMX6SL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(…  in imx6sl_clocks_init()
256 	 * bit 20.  They are used by phy driver to keep the refcount of  in imx6sl_clocks_init()
423 	ret = clk_set_rate(hws[IMX6SL_CLK_AHB]->clk, 132000000);  in imx6sl_clocks_init()
429 		clk_prepare_enable(hws[IMX6SL_CLK_USBPHY1_GATE]->clk);  in imx6sl_clocks_init()
430 		clk_prepare_enable(hws[IMX6SL_CLK_USBPHY2_GATE]->clk);  in imx6sl_clocks_init()
433 	/* Audio-related clocks configuration */  in imx6sl_clocks_init()
434 	clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk);  in imx6sl_clocks_init()
437 	clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk,  in imx6sl_clocks_init()
438 			hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);  in imx6sl_clocks_init()
440 	clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,  in imx6sl_clocks_init()
441 		       hws[IMX6SL_CLK_PLL2_PFD2]->clk);  in imx6sl_clocks_init()
445 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);