Home
last modified time | relevance | path

Searched +full:address +full:- +full:width (Results 1 – 25 of 1047) sorted by relevance

12345678910>>...42

/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
32 /* register address for bitfield rpf_new_rpf_en */
40 /* width of bitfield rpf_new_rpf_en */
51 /* register address for bitfield l2_uc_req_tag0{f}[2:0] */
59 /* width of bitfield l2_uc_req_tag0{f}[2:0] */
69 /* register address for bitfield rpf_l2_bc_req_tag */
77 /* width of bitfield rpf_l2_bc_req_tag */
87 /* register address for bitfield rpf_rss_red1_data[4:0] */
94 /* width of bitfield rpf_rss_red1_data[4:0] */
105 /* register address for bitfield vlan_req_tag0{f}[3:0] */
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
19 addresses in the GMI address space. Should be 2.
[all …]
/linux/drivers/acpi/acpica/
H A Dhwvalid.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: hwvalid - I/O request validation
6 * Copyright (C) 2000 - 2025, Intel Corp.
18 acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width);
22 * conditionally illegal. This table must remain ordered by port address.
37 * RTC: Real-time clock
77 * PARAMETERS: Address Address of I/O port/register
82 * DESCRIPTION: Validates an I/O request (address/length). Certain ports are
90 acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width) in acpi_hw_validate_io_request() argument
109 last_address = address + byte_width - 1; in acpi_hw_validate_io_request()
[all …]
H A Dexregion.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: exregion - ACPI default op_region (address space) handlers
6 * Copyright (C) 2000 - 2025, Intel Corp.
21 * PARAMETERS: function - Read or Write operation
22 * address - Where in the space to read or write
23 * bit_width - Field width in bits (8, 16, or 32)
24 * value - Pointer to in or out value
25 * handler_context - Pointer to Handler's context
26 * region_context - Pointer to context specific to the
31 * DESCRIPTION: Handler for the System Memory address space (Op Region)
[all …]
/linux/drivers/video/
H A Dsticore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/console/sticore.c -
7 * Copyright (C) 2001-2023 Helge Deller <deller@gmx.de>
8 * Copyright (C) 2001-2002 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
11 * - call STI in virtual mode rather than in real mode
12 * - screen blanking with state_mgmt() in text mode STI ?
13 * - try to make it work on m68k hp workstations ;)
29 #include <asm/parisc-device.h>
48 if (IS_ENABLED(CONFIG_64BIT) && sti->do_call64) { in store_sti_val()
49 /* used for 64-bit STI ROM */ in store_sti_val()
[all …]
/linux/include/media/
H A Dv4l2-cci.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
20 * @reg: Register address, use CCI_REG#() macros to encode reg width
31 * Macros to define register address with the register width encoded
59 * cci_read() - Read a value from a single CCI register
62 * @reg: Register address to read, use CCI_REG#() macros to encode reg width
72 * cci_write() - Write a value to a single CCI register
75 * @reg: Register address to write, use CCI_REG#() macros to encode reg width
85 * cci_update_bits() - Perform a read/modify/write cycle on
89 * @reg: Register address to update, use CCI_REG#() macros to encode reg width
[all …]
/linux/arch/arm64/boot/dts/realtek/
H A Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
H A Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
[all …]
H A Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
/linux/arch/powerpc/kernel/
H A Dbtext.c1 // SPDX-License-Identifier: GPL-2.0
74 * The display is mapped to virtual address 0xD0000000, rather
107 * call before the logical address becomes unusable
109 void __init btext_setup_display(int width, int height, int depth, int pitch, in btext_setup_display() argument
110 unsigned long address) in btext_setup_display() argument
114 g_max_loc_X = width / 8; in btext_setup_display()
116 logicalDisplayBase = (unsigned char *)address; in btext_setup_display()
117 dispDeviceBase = (unsigned char *)address; in btext_setup_display()
121 dispDeviceRect[2] = width; in btext_setup_display()
136 * - build some kind of vgacon with it to enable early printk
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
H A Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
[all …]
H A Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls2088a.dtsi"
17 compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
25 stdout-path = "serial1:115200n8";
33 compatible = "jedec,spi-nor";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 spi-max-frequency = <3000000>;
51 #address-cells = <1>;
[all …]
/linux/tools/testing/selftests/kvm/lib/loongarch/
H A Dprocessor.c1 // SPDX-License-Identifier: GPL-2.0
22 shift = level * (vm->page_shift - 3) + vm->page_shift; in virt_pte_index()
23 mask = (1UL << (vm->page_shift - 3)) - 1; in virt_pte_index()
29 return entry & ~((0x1UL << vm->page_shif in pte_addr()
272 int width; loongarch_vcpu_setup() local
[all...]
/linux/include/video/
H A Ds1d13xxxfb.h4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
58 #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c34 hubp2->hubp_regs->reg
37 hubp2->base.ctx
41 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
44 const struct dc_plane_address address) in hubp401_program_3dlut_fl_addr() argument
48 REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part); in hubp401_program_3dlut_fl_addr()
49 REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part); in hubp401_program_3dlut_fl_addr()
82 void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width) in hubp401_program_3dlut_fl_width() argument
86 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width); in hubp401_program_3dlut_fl_width()
136 uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1}; in hubp401_program_3dlut_fl_config()
137 uint32_t width = {cfg->width}; in hubp401_program_3dlut_fl_config() local
[all …]
/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
23 compatible = "ifm,o2d-csi";
[all …]
/linux/drivers/dma/
H A Dfsldma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
108 u32 mr; /* 0x00 - Mode Register */
109 u32 sr; /* 0x04 - Status Register */
110 u64 cdar; /* 0x08 - Current descriptor address register */
111 u64 sar; /* 0x10 - Source Address Register */
112 u64 dar; /* 0x18 - Destination Address Register */
113 u32 bcr; /* 0x20 - Byte Count Register */
114 u64 ndar; /* 0x24 - Next Descriptor Address Register */
130 /* Define macros for fsldma_chan->feature property */
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810_accel.c1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_accel.c -- Hardware Acceleration
26 i810_writel(par->cur_tail, par->iring.virtual, n); \
27 par->cur_tail += 4; \
28 par->cur_tail &= RING_SIZE_MASK; \
51 * wait_for_space - check ring buffer free space
61 struct i810fb_par *par = info->par; in wait_for_space()
63 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_space()
65 tail = par->cur_tail; in wait_for_space()
66 while (count--) { in wait_for_space()
[all …]
/linux/arch/sparc/kernel/
H A Dbtext.c1 // SPDX-License-Identifier: GPL-2.0
42 unsigned int width, height, depth, pitch; in btext_initialize() local
43 unsigned long address = 0; in btext_initialize() local
46 if (prom_getproperty(node, "width", (char *)&width, 4) < 0) in btext_initialize()
47 return -EINVAL; in btext_initialize()
49 return -EINVAL; in btext_initialize()
51 return -EINVAL; in btext_initialize()
52 pitch = width * ((depth + 7) / 8); in btext_initialize()
61 if (prom_getproperty(node, "address", (char *)&prop, 4) >= 0) in btext_initialize()
62 address = prop; in btext_initialize()
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-inventec-starscream.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include "aspeed-g6-pinctrl.dtsi"
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/gpio/aspeed-gpio.h>
13 compatible = "inventec,starscream-bmc", "aspeed,ast2600";
20 stdout-path = &uart5;
28 reserved-memory {
29 #address-cells = <1>;
[all …]
/linux/drivers/staging/sm750fb/
H A Dsm750_accel.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 /* notes: below address are the offset value from de_base_address (0x100000)*/
17 /* type1 data port address is at mmreg_0x110000*/
19 /* for sm712,data port address is at mmreg_0 */
21 /* for sm722,data port address is at mmreg_1mb */
194 u32 x, u32 y, u32 width, u32 height,
199 * @sBase: Address of source: offset in frame buffer
203 * @dBase: Address of destination: offset in frame buffer
208 * @width: width of rectangle in pixel value
217 unsigned int width, unsigned int height,
[all …]
/linux/include/acpi/
H A Dacpiosxf.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: acpiosxf.h - All interfaces to the OS Services Layer (OSL). These
8 * Copyright (C) 2000 - 2025, Intel Corp.
30 #define ACPI_NO_UNIT_LIMIT ((u32) -1)
264 * Platform and hardware-independent I/O interfaces
267 acpi_status acpi_os_read_port(acpi_io_address address, u32 *value, u32 width);
271 acpi_status acpi_os_write_port(acpi_io_address address, u32 value, u32 width);
275 * Platform and hardware-independent physical memory interfaces
277 int acpi_os_read_iomem(void __iomem *virt_addr, u64 *value, u32 width);
281 acpi_os_read_memory(acpi_physical_address address, u64 *value, u32 width);
[all …]

12345678910>>...42