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/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
19 addresses in the GMI address space. Should be 2.
[all …]
/linux/include/media/
H A Dv4l2-cci.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
20 * @reg: Register address, use CCI_REG#() macros to encode reg width
31 * Macros to define register address with the register width encoded
59 * cci_read() - Read a value from a single CCI register
62 * @reg: Register address to read, use CCI_REG#() macros to encode reg width
72 * cci_write() - Write a value to a single CCI register
75 * @reg: Register address to write, use CCI_REG#() macros to encode reg width
85 * cci_update_bits() - Perform a read/modify/write cycle on
89 * @reg: Register address to update, use CCI_REG#() macros to encode reg width
[all …]
/linux/arch/arm64/boot/dts/realtek/
H A Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
H A Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
H A Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
[all …]
H A Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls2088a.dtsi"
17 compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
25 stdout-path = "serial1:115200n8";
33 compatible = "jedec,spi-nor";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 spi-max-frequency = <3000000>;
51 #address-cells = <1>;
[all …]
/linux/arch/powerpc/kernel/
H A Dbtext.c1 // SPDX-License-Identifier: GPL-2.0
74 * The display is mapped to virtual address 0xD0000000, rather
107 * call before the logical address becomes unusable
109 void __init btext_setup_display(int width, int height, int depth, int pitch, in btext_setup_display() argument
110 unsigned long address) in btext_setup_display() argument
114 g_max_loc_X = width / 8; in btext_setup_display()
116 logicalDisplayBase = (unsigned char *)address; in btext_setup_display()
117 dispDeviceBase = (unsigned char *)address; in btext_setup_display()
121 dispDeviceRect[2] = width; in btext_setup_display()
136 * - build some kind of vgacon with it to enable early printk
[all …]
/linux/tools/testing/selftests/kvm/lib/loongarch/
H A Dprocessor.c1 // SPDX-License-Identifier: GPL-2.0
23 shift = level * (vm->page_shift - 3) + vm->page_shift; in virt_pte_index()
24 mask = (1UL << (vm->page_shift - 3)) - 1; in virt_pte_index()
30 return entry & ~((0x1UL << vm->page_shif in pte_addr()
281 int width; loongarch_vcpu_setup() local
[all...]
/linux/include/video/
H A Ds1d13xxxfb.h4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
58 #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
[all …]
/linux/drivers/staging/sm750fb/
H A Dsm750_accel.c1 // SPDX-License-Identifier: GPL-2.0
8 writel(reg_value, accel->dpr_base + offset); in write_dpr()
13 return readl(accel->dpr_base + offset); in read_dpr()
18 writel(data, accel->dp_port_base); in write_dp_port()
75 u32 x, u32 y, u32 width, u32 height, in sm750_hw_fillrect() argument
81 ret = accel->de_wait(); in sm750_hw_fillrect()
108 ((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) | in sm750_hw_fillrect()
122 * @source_base: Address of source: offset in frame buffer
126 * @dest_base: Address of destination: offset in frame buffer
131 * @width: width of rectangle in pixel value
[all …]
H A Dsm750_accel.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 /* notes: below address are the offset value from de_base_address (0x100000) */
17 /* type1 data port address is at mmreg_0x110000 */
19 /* for sm712,data port address is at mmreg_0 */
21 /* for sm722,data port address is at mmreg_1mb */
194 u32 x, u32 y, u32 width, u32 height,
199 * @source_base: Address of source: offset in frame buffer
203 * @dest_base: Address of destination: offset in frame buffer
208 * @width: width of rectangle in pixel value
217 unsigned int width, unsigned int height,
[all …]
/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
23 compatible = "ifm,o2d-csi";
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
/linux/drivers/dma/
H A Dfsldma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
108 u32 mr; /* 0x00 - Mode Register */
109 u32 sr; /* 0x04 - Status Register */
110 u64 cdar; /* 0x08 - Current descriptor address register */
111 u64 sar; /* 0x10 - Source Address Register */
112 u64 dar; /* 0x18 - Destination Address Register */
113 u32 bcr; /* 0x20 - Byte Count Register */
114 u64 ndar; /* 0x24 - Next Descriptor Address Register */
130 /* Define macros for fsldma_chan->feature property */
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810_accel.c1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_accel.c -- Hardware Acceleration
26 i810_writel(par->cur_tail, par->iring.virtual, n); \
27 par->cur_tail += 4; \
28 par->cur_tail &= RING_SIZE_MASK; \
51 * wait_for_space - check ring buffer free space
61 struct i810fb_par *par = info->par; in wait_for_space()
63 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_space()
65 tail = par->cur_tail; in wait_for_space()
66 while (count--) { in wait_for_space()
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dorion-nand.txt4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
16 address space. See mtd.yaml for more detail.
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
H A Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
20 kept in Hi-Z (tristate) after the start of a write access.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-inventec-starscream.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include "aspeed-g6-pinctrl.dtsi"
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/gpio/aspeed-gpio.h>
13 compatible = "inventec,starscream-bmc", "aspeed,ast2600";
20 stdout-path = &uart5;
28 reserved-memory {
29 #address-cells = <1>;
[all …]
/linux/arch/sparc/kernel/
H A Dbtext.c1 // SPDX-License-Identifier: GPL-2.0
42 unsigned int width, height, depth, pitch; in btext_initialize() local
43 unsigned long address = 0; in btext_initialize() local
46 if (prom_getproperty(node, "width", (char *)&width, 4) < 0) in btext_initialize()
47 return -EINVAL; in btext_initialize()
49 return -EINVAL; in btext_initialize()
51 return -EINVAL; in btext_initialize()
52 pitch = width * ((depth + 7) / 8); in btext_initialize()
61 if (prom_getproperty(node, "address", (char *)&prop, 4) >= 0) in btext_initialize()
62 address = prop; in btext_initialize()
[all …]
/linux/drivers/staging/fbtft/
H A Dfb_tls8204.c1 // SPDX-License-Identifier: GPL-2.0+
22 #define WIDTH 84 macro
24 #define TXBUFLEN WIDTH
31 MODULE_PARM_DESC(bs, "BS[2:0] Bias voltage level: 0-7 (default: 4)");
35 par->fbtftops.reset(par); in init_display()
39 * 2:0 PD - Powerdown control: chip is active in init_display()
40 * 1:0 V - Entry mode: horizontal addressing in init_display()
41 * 0:1 H - Extended instruction set control: in init_display()
49 * 2:x BS2 - Bias System in init_display()
54 /* Set the address of the first display line. */ in init_display()
[all …]
/linux/drivers/media/usb/gspca/m5602/
H A Dm5602_po1030.c1 // SPDX-License-Identifier: GPL-2.0-only
99 /* Set the width to 751 */
168 return -ENODEV; in po1030_probe()
173 /* Run the pre-init to actually probe the unit */ in po1030_probe()
187 return -ENODEV; in po1030_probe()
193 return -ENODEV; in po1030_probe()
196 sd->gspca_dev.cam.cam_mode = po1030_modes; in po1030_probe()
197 sd->gspca_dev.cam.nmodes = ARRAY_SIZE(po1030_modes); in po1030_probe()
225 return -EINVAL; in po1030_init()
239 struct v4l2_ctrl_handler *hdl = &sd->gspca_dev.ctrl_handler; in po1030_init_controls()
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_cpplib.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
33 * nfp_cpp_readl() - Read a u32 word from a CPP location
36 * @address: Address for operation
39 * Return: 0 on success, or -ERRNO
42 unsigned long long address, u32 *value) in nfp_cpp_readl() argument
47 n = nfp_cpp_read(cpp, cpp_id, address, tmp, sizeof(tmp)); in nfp_cpp_readl()
49 return n < 0 ? n : -EIO; in nfp_cpp_readl()
56 * nfp_cpp_writel() - Write a u32 word to a CPP location
59 * @address: Address for operation
[all …]
/linux/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
9 #include <dt-bindings/clock/clock.h>
17 * top-level framework. Custom flags for dealing with hardware specifics
20 * * CLK_SET_RATE_GATE - must be gated across rate change
21 * * CLK_SET_PARENT_GATE - must be gated across re-parent
22 * * CLK_SET_RATE_PARENT - propagate rate change up one level
23 * * CLK_IGNORE_UNUSED - do not gate even if unused
24 * * CLK_GET_RATE_NOCACHE - do not use the cached clk rate
[all …]

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