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/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json581 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
586 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
600 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
605 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
610 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
615 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
620 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
625 "PublicDescription": "RD_CAS Access t
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/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json543 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
548 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
553 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
558 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
562 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
567 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
572 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
577 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
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/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json572 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
577 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
601 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
606 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
611 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
616 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
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/linux/Documentation/devicetree/bindings/access-controllers/
H A Daccess-controllers.yaml4 $id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml#
7 title: Generic Domain Access Controllers
13 Common access controllers properties
15 Access controllers are in charge of stating which of the hardware blocks under
18 or a group of hardware blocks. An access controller's domain is the set of
19 resources covered by the access controller.
21 This device tree binding can be used to bind devices to their access
22 controller provided by access-controllers property. In this case, the device
23 is a consumer and the access controller is the provider.
25 An access controller can be represented by any node in the device tree and
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/linux/Documentation/admin-guide/LSM/
H A DSmack.rst9 Smack is the Simplified Mandatory Access Control Kernel.
10 Smack is a kernel based implementation of mandatory access
13 Smack is not the only Mandatory Access Control scheme
14 available for Linux. Those new to Mandatory Access Control
33 access to systems that use them as Smack does.
50 load the Smack access rules
53 report if a process with one label has access
85 Used to make access control decisions. In almost all cases
95 label does not allow all of the access permitted to a process
102 the Smack rule (more below) that permitted the write access
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/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json8 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
52 … the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
102 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
122 …"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a …
142 …"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due…
643 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
653 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
662 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
672 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
682 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
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/linux/drivers/iommu/iommufd/
H A Ddevice.c1017 * a valid cur_ioas (access->ioas). A caller passing in a valid new_ioas should
1020 static int iommufd_access_change_ioas(struct iommufd_access *access, in iommufd_access_change_ioas() argument
1023 u32 iopt_access_list_id = access->iopt_access_list_id; in iommufd_access_change_ioas()
1024 struct iommufd_ioas *cur_ioas = access->ioas; in iommufd_access_change_ioas()
1027 lockdep_assert_held(&access->ioas_lock); in iommufd_access_change_ioas()
1030 if (cur_ioas != access->ioas_unpin) in iommufd_access_change_ioas()
1038 * iommufd_access_unpin_pages() can continue using access->ioas_unpin. in iommufd_access_change_ioas()
1040 access->ioas = NULL; in iommufd_access_change_ioas()
1043 rc = iopt_add_access(&new_ioas->iopt, access); in iommufd_access_change_ioas()
1045 access->ioas = cur_ioas; in iommufd_access_change_ioas()
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/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json8 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
52 … the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
102 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
122 …"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a …
142 …"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due…
1019 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
1029 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
1038 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
1048 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
1058 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h123 * @reg: FAU atomic register to access. 0 <= reg < 2048.
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
143 * @reg: FAU atomic register to access. 0 <= reg < 2048.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
146 * - Step by 8 for 64 bit access.
148 * Note: When performing 32 and 64 bit access, only the low
164 * @reg: FAU atomic register to access. 0 <= reg < 2048.
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/linux/tools/testing/selftests/bpf/verifier/
H A Ddirect_value_access.c2 "direct map access, write test 1",
14 "direct map access, write test 2",
26 "direct map access, write test 3",
38 "direct map access, write test 4",
50 "direct map access, write test 5",
62 "direct map access, write test 6",
75 "direct map access, write test 7",
87 "direct map access, write test 8",
99 "direct map access, write test 9",
108 .errstr = "invalid access to map value pointer",
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H A Dctx_skb.c2 "access skb fields ok",
33 "access skb fields bad1",
38 .errstr = "invalid bpf_context access",
42 "access skb fields bad2",
63 "access skb fields bad3",
85 "access skb fields bad4",
108 "invalid access __sk_buff family",
114 .errstr = "invalid bpf_context access",
118 "invalid access __sk_buff remote_ip4",
124 .errstr = "invalid bpf_context access",
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/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A Duncore-cache.json3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
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/linux/include/linux/
H A Dkcsan-checks.h3 * KCSAN access checks and modifiers. These can be used to explicitly check
16 /* Access types -- if KCSAN_ACCESS_WRITE is not set, the access is a read. */
17 #define KCSAN_ACCESS_WRITE (1 << 0) /* Access is a write. */
19 #define KCSAN_ACCESS_ATOMIC (1 << 2) /* Access is atomic. */
21 #define KCSAN_ACCESS_ASSERT (1 << 3) /* Access is an assertion. */
22 #define KCSAN_ACCESS_SCOPED (1 << 4) /* Access is a scoped access. */
27 * to validate access to an address. Never use these in header files!
31 * __kcsan_check_access - check generic access for races
33 * @ptr: address of access
34 * @size: size of access
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/linux/security/landlock/
H A Daudit.c15 #include "access.h"
89 const access_mask_t access) in log_blockers() argument
91 const unsigned long access_mask = access; in log_blockers()
95 for_each_set_bit(access_bit, &access_mask, BITS_PER_TYPE(access)) { in log_blockers()
230 access_mask_t access; in test_get_denied_layer() local
232 access = LANDLOCK_ACCESS_FS_EXECUTE; in test_get_denied_layer()
234 get_denied_layer(&dom, &access, &layer_masks, in test_get_denied_layer()
236 KUNIT_EXPECT_EQ(test, access, LANDLOCK_ACCESS_FS_EXECUTE); in test_get_denied_layer()
238 access = LANDLOCK_ACCESS_FS_READ_FILE; in test_get_denied_layer()
240 get_denied_layer(&dom, &access, &layer_masks, in test_get_denied_layer()
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/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Duncore-cache.json3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
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/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-memory.json542 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
551 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
560 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
569 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
578 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
587 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
596 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
605 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
614 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
623 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
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/linux/Documentation/core-api/
H A Dunaligned-memory-access.rst14 when it comes to memory access. This document presents some details about
19 The definition of an unaligned access
26 access.
28 The above may seem a little vague, as memory access can happen in different
32 which will compile to multiple-byte memory access instructions, namely when
47 of memory access. However, we must consider ALL supported architectures;
52 Why unaligned access is bad
55 The effects of performing an unaligned memory access vary from architecture
62 happen. The exception handler is able to correct the unaligned access,
66 unaligned access to be corrected.
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/linux/tools/testing/selftests/bpf/progs/
H A Dverifier_helper_value_access.c42 __description("helper access to map: full range")
68 __description("helper access to map: partial range")
98 __description("helper access to map: empty range")
125 __description("helper access to map: possibly-empty ange")
154 __description("helper access to map: out-of-bound range")
155 __failure __msg("invalid access to map value, value_size=48 off=0 size=56")
180 __description("helper access to map: negative range")
205 __description("helper access to adjusted map (via const imm): full range")
233 __description("helper access to adjusted map (via const imm): partial range")
260 __description("helper access to adjusted map (via const imm): empty range")
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H A Dverifier_direct_packet_access.c25 __description("direct packet access: test1")
45 __description("direct packet access: test2")
80 __description("direct packet access: test3")
81 __failure __msg("invalid bpf_context access off=76")
95 __description("direct packet access: test4 (write)")
115 __description("direct packet access: test5 (pkt_end >= reg, good access)")
137 __description("direct packet access: test6 (pkt_end >= reg, bad access)")
138 __failure __msg("invalid access to packet")
159 __description("direct packet access: test7 (pkt_end >= reg, both accesses)")
160 __failure __msg("invalid access to packet")
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json153 …"PublicDescription": "Level 2 TLB last-level walk cache access. This event does not count if the M…
156 …"BriefDescription": "Level 2 TLB last-level walk cache access. This event does not count if the MM…
165 …"PublicDescription": "Level 2 TLB level-2 walk cache access. This event counts accesses to the lev…
168 …"BriefDescription": "Level 2 TLB level-2 walk cache access. This event counts accesses to the leve…
177 …he access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to m…
180 …he access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to m…
183 …a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a ref…
186 …a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a ref…
195 … 2 data cache access. This event occurs when a requestor outside the PE makes a coherency request …
198 … 2 data cache access. This event occurs when a requestor outside the PE makes a coherency request …
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/linux/Documentation/mm/damon/
H A Ddesign.rst32 overhead/accuracy control and access-aware system operations on top of the
46 For data access monitoring and additional low level work, DAMON needs a set of
48 the given target address space. For example, below two operations for access
52 2. Access check of specific address range in the target space.
67 Also, if some architectures or devices support special optimized access check
121 PTE Accessed-bit Based Access Check
125 Accessed-bit for basic access checks. Only one difference is the way of
159 Access Frequency Monitoring
163 duration. The resolution of the access frequency is controlled by setting
165 access to each page per ``sampling interval`` and aggregates the results. In
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/linux/drivers/infiniband/sw/rxe/
H A Drxe_mw.c51 struct rxe_mw *mw, struct rxe_mr *mr, int access) in rxe_check_bind_mw() argument
61 if (unlikely((access & IB_ZERO_BASED))) { in rxe_check_bind_mw()
94 if (unlikely(mr->access & IB_ZERO_BASED)) { in rxe_check_bind_mw()
100 if (unlikely(!(mr->access & IB_ACCESS_MW_BIND))) { in rxe_check_bind_mw()
102 "attempt to bind an MW to an MR without bind access\n"); in rxe_check_bind_mw()
107 if (unlikely((access & in rxe_check_bind_mw()
109 !(mr->access & IB_ACCESS_LOCAL_WRITE))) { in rxe_check_bind_mw()
111 "attempt to bind an Writable MW to an MR without local write access\n"); in rxe_check_bind_mw()
116 if (access & IB_ZERO_BASED) { in rxe_check_bind_mw()
136 struct rxe_mw *mw, struct rxe_mr *mr, int access) in rxe_do_bind_mw() argument
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/linux/tools/testing/selftests/landlock/
H A Dfs_test.c440 * (access type) confusion for this test. in test_open_rel()
541 /* Tests with denied-by-default access right. */ in TEST_F_FORK()
555 /* Test with no access. */ in TEST_F_FORK()
600 __u64 access; in TEST_F_FORK() local
612 /* Tests access rights for files. */ in TEST_F_FORK()
616 /* Tests access rights for directories. */ in TEST_F_FORK()
621 for (access = 1; access <= ACCESS_LAST; access <<= 1) { in TEST_F_FORK()
622 path_beneath_dir.allowed_access = access; in TEST_F_FORK()
627 path_beneath_file.allowed_access = access; in TEST_F_FORK()
630 if (access & ACCESS_FILE) { in TEST_F_FORK()
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-catu.h43 * sectionA4.7 Access Permissions.
45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
47 * Bit 2: 0 - Data access, 1 - instruction access.
49 * CATU AXICTRL:ARPROT[2] is res0 as we always access data.
75 return csdev_access_relaxed_read32(&drvdata->csdev->access, offset); \
80 csdev_access_relaxed_write32(&drvdata->csdev->access, val, offset); \
87 return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \
92 csdev_access_relaxed_write_pair(&drvdata->csdev->access, val, lo_off, hi_off); \
/linux/security/
H A Ddevice_cgroup.c38 short access; member
118 walk->access |= ex->access; in dev_exception_add()
146 walk->access &= ~ex->access; in dev_exception_rm()
147 if (!walk->access) { in dev_exception_rm()
250 static void set_access(char *acc, short access) in set_access() argument
254 if (access & DEVCG_ACC_READ) in set_access()
256 if (access & DEVCG_ACC_WRITE) in set_access()
258 if (access & DEVCG_ACC_MKNOD) in set_access()
302 set_access(acc, ex->access); in devcgroup_seq_show()
320 * @access: permission mask (DEVCG_ACC_READ, DEVCG_ACC_WRITE, DEVCG_ACC_MKNOD)
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