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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_power.c1 /* SPDX-License-Identifier: MIT */
41 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
45 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
209 static bool __intel_display_power_is_enabled(struct intel_display *display, in __intel_display_power_is_enabled()
215 if (intel_display_rpm_suspended(display)) in __intel_display_power_is_enabled()
220 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled()
234 * intel_display_power_is_enabled - check for a power domain
235 * @display
207 __intel_display_power_is_enabled(struct intel_display * display,enum intel_display_power_domain domain) __intel_display_power_is_enabled() argument
248 intel_display_power_is_enabled(struct intel_display * display,enum intel_display_power_domain domain) intel_display_power_is_enabled() argument
262 sanitize_target_dc_state(struct intel_display * display,u32 target_dc_state) sanitize_target_dc_state() argument
296 intel_display_power_set_target_dc_state(struct intel_display * display,u32 state) intel_display_power_set_target_dc_state() argument
339 intel_display_power_get_current_dc_state(struct intel_display * display) intel_display_power_get_current_dc_state() argument
374 struct intel_display *display = container_of(power_domains, assert_async_put_domain_masks_disjoint() local
387 struct intel_display *display = container_of(power_domains, __async_put_domains_state_ok() local
410 struct intel_display *display = container_of(power_domains, print_power_domains() local
425 struct intel_display *display = container_of(power_domains, print_async_put_domains_state() local
490 intel_display_power_grab_async_put_ref(struct intel_display * display,enum intel_display_power_domain domain) intel_display_power_grab_async_put_ref() argument
519 __intel_display_power_get_domain(struct intel_display * display,enum intel_display_power_domain domain) __intel_display_power_get_domain() argument
546 intel_display_power_get(struct intel_display * display,enum intel_display_power_domain domain) intel_display_power_get() argument
574 intel_display_power_get_if_enabled(struct intel_display * display,enum intel_display_power_domain domain) intel_display_power_get_if_enabled() argument
605 __intel_display_power_put_domain(struct intel_display * display,enum intel_display_power_domain domain) __intel_display_power_put_domain() argument
628 __intel_display_power_put(struct intel_display * display,enum intel_display_power_domain domain) __intel_display_power_put() argument
643 struct intel_display *display = container_of(power_domains, queue_async_put_domains_work() local
657 struct intel_display *display = container_of(power_domains, release_async_put_domains() local
677 struct intel_display *display = container_of(work, struct intel_display, intel_display_power_put_async_work() local
740 __intel_display_power_put_async(struct intel_display * display,enum intel_display_power_domain domain,intel_wakeref_t wakeref,int delay_ms) __intel_display_power_put_async() argument
797 intel_display_power_flush_work(struct intel_display * display) intel_display_power_flush_work() argument
830 intel_display_power_flush_work_sync(struct intel_display * display) intel_display_power_flush_work_sync() argument
853 intel_display_power_put(struct intel_display * display,enum intel_display_power_domain domain,intel_wakeref_t wakeref) intel_display_power_put() argument
874 intel_display_power_put_unchecked(struct intel_display * display,enum intel_display_power_domain domain) intel_display_power_put_unchecked() argument
883 intel_display_power_get_in_set(struct intel_display * display,struct intel_display_power_domain_set * power_domain_set,enum intel_display_power_domain domain) intel_display_power_get_in_set() argument
899 intel_display_power_get_in_set_if_enabled(struct intel_display * display,struct intel_display_power_domain_set * power_domain_set,enum intel_display_power_domain domain) intel_display_power_get_in_set_if_enabled() argument
920 intel_display_power_put_mask_in_set(struct intel_display * display,struct intel_display_power_domain_set * power_domain_set,struct intel_power_domain_mask * mask) intel_display_power_put_mask_in_set() argument
949 get_allowed_dc_mask(struct intel_display * display,int enable_dc) get_allowed_dc_mask() argument
1026 intel_power_domains_init(struct intel_display * display) intel_power_domains_init() argument
1052 intel_power_domains_cleanup(struct intel_display * display) intel_power_domains_cleanup() argument
1057 intel_power_domains_sync_hw(struct intel_display * display) intel_power_domains_sync_hw() argument
1068 gen9_dbuf_slice_set(struct intel_display * display,enum dbuf_slice slice,bool enable) gen9_dbuf_slice_set() argument
1085 gen9_dbuf_slices_update(struct intel_display * display,u8 req_slices) gen9_dbuf_slices_update() argument
1116 gen9_dbuf_enable(struct intel_display * display) gen9_dbuf_enable() argument
1134 gen9_dbuf_disable(struct intel_display * display) gen9_dbuf_disable() argument
1142 gen12_dbuf_slices_config(struct intel_display * display) gen12_dbuf_slices_config() argument
1152 icl_mbus_init(struct intel_display * display) icl_mbus_init() argument
1181 hsw_assert_cdclk(struct intel_display * display) hsw_assert_cdclk() argument
1201 assert_can_disable_lcpll(struct intel_display * display) assert_can_disable_lcpll() argument
1252 hsw_read_dcomp(struct intel_display * display) hsw_read_dcomp() argument
1260 hsw_write_dcomp(struct intel_display * display,u32 val) hsw_write_dcomp() argument
1279 hsw_disable_lcpll(struct intel_display * display,bool switch_to_fclk,bool allow_power_down) hsw_disable_lcpll() argument
1330 hsw_restore_lcpll(struct intel_display * display) hsw_restore_lcpll() argument
1406 hsw_enable_pc8(struct intel_display * display) hsw_enable_pc8() argument
1418 hsw_disable_pc8(struct intel_display * display) hsw_disable_pc8() argument
1433 intel_pch_reset_handshake(struct intel_display * display,bool enable) intel_pch_reset_handshake() argument
1453 skl_display_core_init(struct intel_display * display,bool resume) skl_display_core_init() argument
1486 skl_display_core_uninit(struct intel_display * display) skl_display_core_uninit() argument
1520 bxt_display_core_init(struct intel_display * display,bool resume) bxt_display_core_init() argument
1554 bxt_display_core_uninit(struct intel_display * display) bxt_display_core_uninit() argument
1616 tgl_bw_buddy_init(struct intel_display * display) tgl_bw_buddy_init() argument
1659 icl_display_core_init(struct intel_display * display,bool resume) icl_display_core_init() argument
1741 icl_display_core_uninit(struct intel_display * display) icl_display_core_uninit() argument
1778 chv_phy_control_init(struct intel_display * display) chv_phy_control_init() argument
1865 vlv_cmnlane_wa(struct intel_display * display) vlv_cmnlane_wa() argument
1893 vlv_punit_is_power_gated(struct intel_display * display,u32 reg0) vlv_punit_is_power_gated() argument
1904 assert_ved_power_gated(struct intel_display * display) assert_ved_power_gated() argument
1911 assert_isp_power_gated(struct intel_display * display) assert_isp_power_gated() argument
1942 intel_power_domains_init_hw(struct intel_display * display,bool resume) intel_power_domains_init_hw() argument
2004 intel_power_domains_driver_remove(struct intel_display * display) intel_power_domains_driver_remove() argument
2032 intel_power_domains_sanitize_state(struct intel_display * display) intel_power_domains_sanitize_state() argument
2065 intel_power_domains_enable(struct intel_display * display) intel_power_domains_enable() argument
2081 intel_power_domains_disable(struct intel_display * display) intel_power_domains_disable() argument
2103 intel_power_domains_suspend(struct intel_display * display,bool s2idle) intel_power_domains_suspend() argument
2156 intel_power_domains_resume(struct intel_display * display) intel_power_domains_resume() argument
2172 intel_power_domains_dump_info(struct intel_display * display) intel_power_domains_dump_info() argument
2200 intel_power_domains_verify_state(struct intel_display * display) intel_power_domains_verify_state() argument
2254 intel_power_domains_verify_state(struct intel_display * display) intel_power_domains_verify_state() argument
2260 intel_display_power_suspend_late(struct intel_display * display,bool s2idle) intel_display_power_suspend_late() argument
2276 intel_display_power_resume_early(struct intel_display * display) intel_display_power_resume_early() argument
2293 intel_display_power_suspend(struct intel_display * display) intel_display_power_suspend() argument
2306 intel_display_power_resume(struct intel_display * display) intel_display_power_resume() argument
2330 intel_display_power_debug(struct intel_display * display,struct seq_file * m) intel_display_power_debug() argument
2480 intel_port_domains_for_platform(struct intel_display * display,const struct intel_ddi_port_domains ** domains,int * domains_size) intel_port_domains_for_platform() argument
2500 intel_port_domains_for_port(struct intel_display * display,enum port port) intel_port_domains_for_port() argument
2515 intel_display_power_ddi_io_domain(struct intel_display * display,enum port port) intel_display_power_ddi_io_domain() argument
2526 intel_display_power_ddi_lanes_domain(struct intel_display * display,enum port port) intel_display_power_ddi_lanes_domain() argument
2537 intel_port_domains_for_aux_ch(struct intel_display * display,enum aux_ch aux_ch) intel_port_domains_for_aux_ch() argument
2552 intel_display_power_aux_io_domain(struct intel_display * display,enum aux_ch aux_ch) intel_display_power_aux_io_domain() argument
2563 intel_display_power_legacy_aux_domain(struct intel_display * display,enum aux_ch aux_ch) intel_display_power_legacy_aux_domain() argument
2574 intel_display_power_tbt_aux_domain(struct intel_display * display,enum aux_ch aux_ch) intel_display_power_tbt_aux_domain() argument
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H A Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 #include <linux/dma-resv.h>
35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/display/drm_dp_tunnel.h>
147 return (crtc_state->active_planes & in is_hdr_mode()
151 /* WA Display #0827: Gen9:all */
153 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) in skl_wa_827() argument
155 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in skl_wa_827()
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H A Dintel_dmc.c4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
49 * engine to save and restore the state of display engine when it enter into
50 * low-power state and comes back to normal.
53 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git"
65 struct intel_display *display; member
87 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
89 return display in display_to_dmc()
92 dmc_firmware_param(struct intel_display * display) dmc_firmware_param() argument
99 dmc_firmware_param_disabled(struct intel_display * display) dmc_firmware_param_disabled() argument
185 dmc_firmware_default(struct intel_display * display,u32 * size) dmc_firmware_default() argument
403 has_dmc_id_fw(struct intel_display * display,enum intel_dmc_id dmc_id) has_dmc_id_fw() argument
410 intel_dmc_has_payload(struct intel_display * display) intel_dmc_has_payload() argument
416 intel_get_stepping_info(struct intel_display * display,struct stepping_info * si) intel_get_stepping_info() argument
426 gen9_set_dc_state_debugmask(struct intel_display * display) gen9_set_dc_state_debugmask() argument
434 disable_event_handler(struct intel_display * display,i915_reg_t ctl_reg,i915_reg_t htp_reg) disable_event_handler() argument
445 disable_all_event_handlers(struct intel_display * display,enum intel_dmc_id dmc_id) disable_all_event_handlers() argument
463 adlp_pipedmc_clock_gating_wa(struct intel_display * display,bool enable) adlp_pipedmc_clock_gating_wa() argument
484 mtl_pipedmc_clock_gating_wa(struct intel_display * display) mtl_pipedmc_clock_gating_wa() argument
496 pipedmc_clock_gating_wa(struct intel_display * display,bool enable) pipedmc_clock_gating_wa() argument
504 pipedmc_interrupt_mask(struct intel_display * display) pipedmc_interrupt_mask() argument
524 is_dmc_evt_ctl_reg(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg) is_dmc_evt_ctl_reg() argument
534 is_dmc_evt_htp_reg(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg) is_dmc_evt_htp_reg() argument
544 is_event_handler(struct intel_display * display,enum intel_dmc_id dmc_id,unsigned int event_id,i915_reg_t reg,u32 data) is_event_handler() argument
553 fixup_dmc_evt(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg_ctl,u32 * data_ctl,i915_reg_t reg_htp,u32 * data_htp) fixup_dmc_evt() argument
583 disable_dmc_evt(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg,u32 data) disable_dmc_evt() argument
607 dmc_mmiodata(struct intel_display * display,struct intel_dmc * dmc,enum intel_dmc_id dmc_id,int i) dmc_mmiodata() argument
619 dmc_load_mmio(struct intel_display * display,enum intel_dmc_id dmc_id) dmc_load_mmio() argument
630 dmc_load_program(struct intel_display * display,enum intel_dmc_id dmc_id) dmc_load_program() argument
650 assert_dmc_loaded(struct intel_display * display,enum intel_dmc_id dmc_id) assert_dmc_loaded() argument
685 assert_main_dmc_loaded(struct intel_display * display) assert_main_dmc_loaded() argument
690 need_pipedmc_load_program(struct intel_display * display) need_pipedmc_load_program() argument
696 need_pipedmc_load_mmio(struct intel_display * display,enum pipe pipe) need_pipedmc_load_mmio() argument
744 struct intel_display *display = to_intel_display(crtc_state); can_enable_pipedmc() local
759 struct intel_display *display = to_intel_display(crtc_state); intel_dmc_enable_pipe() local
794 struct intel_display *display = to_intel_display(crtc_state); intel_dmc_disable_pipe() local
815 dmc_configure_event(struct intel_display * display,enum intel_dmc_id dmc_id,unsigned int event_id,bool enable) dmc_configure_event() argument
849 intel_dmc_block_pkgc(struct intel_display * display,enum pipe pipe,bool block) intel_dmc_block_pkgc() argument
867 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display * display,enum pipe pipe,bool enable) intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() argument
883 intel_dmc_load_program(struct intel_display * display) intel_dmc_load_program() argument
921 intel_dmc_disable_program(struct intel_display * display) intel_dmc_disable_program() argument
963 struct intel_display *display = dmc->display; dmc_set_fw_offset() local
993 struct intel_display *display = dmc->display; dmc_mmio_addr_sanity_check() local
1026 struct intel_display *display = dmc->display; parse_dmc_fw_header() local
1168 struct intel_display *display = dmc->display; parse_dmc_fw_package() local
1222 struct intel_display *display = dmc->display; parse_dmc_fw_css() local
1244 struct intel_display *display = dmc->display; parse_dmc_fw() local
1295 intel_dmc_runtime_pm_get(struct intel_display * display) intel_dmc_runtime_pm_get() argument
1301 intel_dmc_runtime_pm_put(struct intel_display * display) intel_dmc_runtime_pm_put() argument
1309 dmc_fallback_path(struct intel_display * display) dmc_fallback_path() argument
1320 struct intel_display *display = dmc->display; dmc_load_work_fn() local
1373 intel_dmc_init(struct intel_display * display) intel_dmc_init() argument
1433 intel_dmc_suspend(struct intel_display * display) intel_dmc_suspend() argument
1448 intel_dmc_wait_fw_load(struct intel_display * display) intel_dmc_wait_fw_load() argument
1466 intel_dmc_resume(struct intel_display * display) intel_dmc_resume() argument
1486 intel_dmc_fini(struct intel_display * display) intel_dmc_fini() argument
1512 intel_dmc_snapshot_capture(struct intel_display * display) intel_dmc_snapshot_capture() argument
1545 intel_dmc_update_dc6_allowed_count(struct intel_display * display,bool start_tracking) intel_dmc_update_dc6_allowed_count() argument
1562 intel_dmc_get_dc6_allowed_count(struct intel_display * display,u32 * count) intel_dmc_get_dc6_allowed_count() argument
1585 struct intel_display *display = m->private; intel_dmc_debugfs_status_show() local
1661 intel_dmc_debugfs_register(struct intel_display * display) intel_dmc_debugfs_register() argument
1667 intel_pipedmc_irq_handler(struct intel_display * display,enum pipe pipe) intel_pipedmc_irq_handler() argument
1713 struct intel_display *display = to_intel_display(crtc); intel_pipedmc_enable_event() local
1722 struct intel_display *display = to_intel_display(crtc); intel_pipedmc_disable_event() local
1730 struct intel_display *display = to_intel_display(crtc); intel_pipedmc_start_mmioaddr() local
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H A Dintel_frontbuffer.c4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
33 * To be able to do so we track frontbuffers using a bitmask for all possible
37 * and when the frontbuffer is exchanged with a flip. Subsystems interested in
42 * On a high level there are two types of powersaving features. The first one
43 * work like a special cache (FBC and PSR) and are interested when they should
51 * The other type of display power saving feature only cares about busyness
72 * frontbuffer_flush - flush frontbuffer
73 * @display: display device
83 static void frontbuffer_flush(struct intel_display *display, in frontbuffer_flush() argument
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H A Dvlv_dsi_regs.h1 /* SPDX-License-Identifier: MIT */
14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ argument
17 #define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) argument
47 #define DPI_ENABLE (1 << 31) /* A + C */
54 #define DITHERING_ENABLE (1 << 25) /* A + C */
75 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
76 #define TEARING_EFFECT_SHIFT 2 /* A + C */
93 /* MIPI DSI Controller and D-PHY registers */
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
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H A Dintel_display_reg_defs.h1 /* SPDX-License-Identifier: MIT */
11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset)
18 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument
19 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) argument
20 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) argument
21 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) argument
22 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) argument
23 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) argument
25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
26 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) argument
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H A Dintel_psr.c4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
62 * Since Haswell Display controller supports Panel Self-Refresh on display
63 * panels witch have a remote frame buffer (RFB) implemented according to PSR
64 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
65 * when system is idle but display is on as it eliminates display refresh
67 * display is unchanged.
76 * The implementation uses the hardware-based PSR support which automatically
77 * enters/exits self-refresh mode. The hardware takes care of sending the
80 * changes to know when to exit self-refresh mode again. Unfortunately that
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H A Dintel_fb.c1 // SPDX-License-Identifier: MIT
6 #include <linux/dma-fence.h>
7 #include <linux/dma-resv.h>
26 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) argument
31 * the cache-line pairs. The compression state of the cache-line pair
32 * is specified by 2 bits in the CCS. Each CCS cache-line represents
33 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
34 * cache-line-pairs. CCS is always Y tiled."
39 * us a ratio of one byte in the CCS for each 8x16 pixels in the
62 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
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H A Dintel_opregion.h2 * Copyright © 2008-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
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H A Dintel_display_device.h1 /* SPDX-License-Identifier: MIT */
20 * Display platforms and subplatforms. Keep platforms in display version based
21 * order, chronological order within a version, and subplatforms next to the
29 /* Display ver 2 */ \
34 /* Display ver 3 */ \
41 /* Display ver 4 */ \
46 /* Display ver 5 */ \
48 /* Display ve
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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
20 synthesis time. As a result, many of the device-tree bindings are meant to
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H A Datmel,lcdc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip's LCDC Display
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
15 from an external display buffer to a TFT LCD panel. The LCDC has one display
17 interface and a look-up table to allow palletized display configurations. The
18 LCDC is programmable on a per layer basis, and supports different LCD
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/linux/Documentation/gpu/
H A Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
30 The various host1x clients need to be bound together into a logical device in
32 this is implemented in the host1x driver. When a driver is registered with the
33 infrastructure it provides a list of compatible strings specifying the devices
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H A Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
4 drm/komeda Arm display driver
7 The drm/komeda driver supports the Arm display processor D71 and later products,
8 this document gives a brief overview of driver design: how it works and why
11 Overview of D71 like display IPs
14 From D71, Arm display IP begins to adopt a flexible and modularized
15 architecture. A display pipeline is made up of multiple individual and
17 specific capabilities that can give the flowed pipeline pixel data a
23 -----
30 ------
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/linux/drivers/auxdisplay/
H A Dline-display.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Character line display core support
9 * Copyright (C) 2025 Jean-François Lessard
33 #include "line-display.h"
38 * struct linedisp_attachment - Hold
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/linux/include/drm/
H A Dgud.h1 /* SPDX-License-Identifier: MIT */
12 * struct gud_display_descriptor_req - Display descriptor
16 * - STATUS_ON_SET: Always do a status request after a SET request.
18 * no way to control the status stage of a control OUT
19 * request that has a payload.
20 * - FULL_UPDATE: Always send the entire framebuffer when flushing changes.
24 * a chance to reset its state machine if needed.
27 * - GUD_COMPRESSION_LZ4: LZ4 lossless compression.
29 * This is useful for devices that don't have a big enough
36 * Devices that have only one display mode will have min_width == max_width
[all …]
/linux/Documentation/gpu/amdgpu/display/
H A Dmpo-overview.rst6 'Documentation/gpu/amdgpu/display/dcn-overview.rst'.
10 fixed-function hardware in the display controller rather than using graphics or
12 the graphics/compute pipelines can be put into low-power states. In summary,
15 * Decreased GPU and CPU workload - no composition shaders needed, no extra
17 * Plane independent page flips - No need to be tied to global compositor
18 page-flip present rate, reduced latency, independent timing.
20 .. note:: Keep in mind that MPO is all about power-saving; if you want to learn
21 more about power-save in the display context, check the link:
22 `Power <https://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rst>`__.
25 model only uses a single userspace IOCTL for configuring the display hardware
[all …]
H A Ddisplay-manager.rst2 AMDgpu Display Manager
8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-colorimetry.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _colorimetry-controls:
16 -----------------------
18 .. _colorimetry-control-id:
23 return a description of this control class.
33 .. flat-table:: struct v4l2_ctrl_hdr10_cll_info
34 :header-rows: 0
35 :stub-columns: 0
38 * - __u16
39 - ``max_content_light_level``
[all …]
/linux/tools/perf/Documentation/
H A Dperf-c2c.txt1 perf-c2c(1)
5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer.
9 --------
12 'perf c2c record' [<options>] \-- [<record command options>] <command>
16 -----------
27 required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the
32 - memory address of the access
33 - type of the access (load and store details)
34 - latency (in cycles) of the load access
[all …]
/linux/Documentation/arch/arm/omap/
H A Ddss.rst2 OMAP2/3 Display Subsystem
7 TV-out and multiple display support, but there are lots of small improvements
10 The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
15 --------
19 - MIPI DPI (parallel) output
20 - MIPI DSI output in command mode
21 - MIPI DBI (RFBI) output
22 - SDI output
23 - TV output
24 - All pieces can be compiled as a module or inside kernel
[all …]
/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-simple.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
14 This binding file is a collection of the simple (dumb) panels that
15 requires only a single power-supply.
16 There are optionally a backlight and an enable GPIO.
17 The panel may use an OF graph binding for the association to the display,
[all …]
/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dmodtronix,lcd2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Modtronix engineering LCD2S Character LCD Display
10 - Lars Poeschel <poeschel@lemonage.de>
13 The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
14 The display supports a serial I2C and SPI interface. The driver currently
24 I2C bus address of the display.
26 display-height-chars:
27 description: Height of the display, in character cells.
[all …]
/linux/include/linux/
H A Ddio.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Maybe this should handle DIO-II later?
18 /* The DIO boards in a system are distinguished by 'select codes' which
19 * range from 0-63 (DIO) and 132-255 (DIO-II).
22 * So DIO cards cover [0x600000-0x800000); the areas [0x200000-0x400000) and
23 * [0x800000-0x1000000) are for additional space required by things
24 * like framebuffers. [0x400000-0x600000) is for miscellaneous internal I/O.
27 * DIO-II boards are at 0x1000000 + (sc - 132) * 0x400000
28 * which is address range [0x1000000-0x20000000) -- too big to map completely,
29 * so currently we just don't handle DIO-II boards. It wouldn't be hard to
[all …]
/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_kms.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
4 * Copyright (c) 2009-2025 Broadcom. All Rights Reserved. The term
20 * struct vmw_du_update_plane - Closure structure for vmw_du_helper_plane_update
24 * @du: Display unit on which to update the plane.
25 * @vfb: Framebuffer which is blitted to display unit.
31 * This structure loosely represent the set of operations needed to perform a
32 * plane update on a display unit. Implementer will define that functionality
42 * damage clips on display unit @num_hits will be passed to allocate
54 * like update GB image for proxy surface and define a GMRFB for screen
81 * if needed. This will be called times have damage in display unit,
[all …]

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