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Searched +full:a +full:- +full:display (Results 1 – 25 of 1026) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A D	intel_display_power.c	1 /* SPDX-License-Identifier: MIT / 39 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 43 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 207 static bool __intel_display_power_is_enabled(struct intel_display display, in __intel_display_power_is_enabled() argument 213 if (intel_display_rpm_suspended(display)) in __intel_display_power_is_enabled() 218 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled() 232 * intel_display_power_is_enabled - check for a power domain 233 * @display: display device instance 242 * threads can't disable the power well while the caller tries to read a few 248 bool intel_display_power_is_enabled(struct intel_display *display, in intel_display_power_is_enabled() argument [all …]
H A D	vlv_dsi_regs.h	1 /* SPDX-License-Identifier: MIT / 14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument 16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) / ports A and C only / argument 17 #define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) argument 47 #define DPI_ENABLE (1 << 31) / A + C / 54 #define DITHERING_ENABLE (1 << 25) / A + C / 75 #define TEARING_EFFECT_DELAY (1 << 4) / A + C / 76 #define TEARING_EFFECT_SHIFT 2 / A + C / 93 / MIPI DSI Controller and D-PHY registers */ 97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument [all …]
H A D	intel_display_reg_defs.h	1 /* SPDX-License-Identifier: MIT */ 11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset) 18 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument 19 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) argument 20 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) argument 21 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) argument 22 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) argument 23 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) argument 25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument 26 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) argument [all …]
H A D	intel_opregion.h	2 * Copyright © 2008-2017 Intel Corporation 4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 37 int intel_opregion_setup(struct intel_display display); 38 void intel_opregion_cleanup(struct intel_display display); 40 void intel_opregion_register(struct intel_display display); 41 void intel_opregion_unregister(struct intel_display display); 43 void intel_opregion_resume(struct intel_display display); 44 void intel_opregion_suspend(struct intel_display display, 47 bool intel_opregion_asle_present(struct intel_display *display); [all …]
H A D	intel_cx0_phy.c	1 // SPDX-License-Identifier: MIT 39 struct intel_display display = to_intel_display(encoder); in intel_encoder_is_c10phy() local 42 / PTL doesn't have a PHY connected to PORT B; as such, in intel_encoder_is_c10phy() 43 * there will never be a case where PTL uses PHY B. in intel_encoder_is_c10phy() 44 * WCL uses PORT A and B with the C10 PHY. in intel_encoder_is_c10phy() 48 if (display->platform.pantherlake && phy < PHY_C) in intel_encoder_is_c10phy() 51 if ((display->platform.lunarlake \|\| display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy() 74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask() 75 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask() 82 assert_dc_off(struct intel_display *display) in assert_dc_off() argument [all …]
/linux/Documentation/devicetree/bindings/display/
H A D	simple-framebuffer.yaml	1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Hans de Goede <hdegoede@redhat.com> 13 A simple frame-buffer describes a frame-buffer setup by firmware or 14 the bootloader, with the assumption that the display hardware has 19 sub-nodes of the chosen node (*). Simplefb nodes must be named 22 If the devicetree contains nodes for the display hardware used by a 23 simplefb, then the simplefb node must contain a property called [all …]
H A D	xylon,logicvc-display.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Xylon LogiCVC display controller 11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com> 14 The Xylon LogiCVC is a display controller that supports multiple layers. 16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs. 18 Because the controller is intended for use in a FPGA, most of the 20 synthesis time. As a result, many of the device-tree bindings are meant to [all …]
H A D	atmel,lcdc-display.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip's LCDC Display 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Dharma Balasubiramani <dharma.b@microchip.com> 15 from an external display buffer to a TFT LCD panel. The LCDC has one display 17 interface and a look-up table to allow palletized display configurations. The 18 LCDC is programmable on a per layer basis, and supports different LCD [all …]
H A D	cirrus,clps711x-fb.txt	4 - compatible: Shall contain "cirrus,ep7209-fb". 5 - reg : Physical base address and length of the controller's registers + 7 - clocks : phandle + clock specifier pair of the FB reference clock. 8 - display : phandle to a display node as described in 9 Documentation/devicetree/bindings/display/panel/display-timing.txt. 10 Additionally, the display node has to define properties: 11 - bits-per-pixel: Bits per pixel. 12 - ac-prescale : LCD AC bias frequency. This frequency is the required 13 AC bias frequency for a given manufacturer's LCD plate. 14 - cmap-invert : Invert the color levels (Optional). [all …]
H A D	atmel,lcdc.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/atmel,lcdc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Dharma Balasubiramani <dharma.b@microchip.com> 14 The LCDC works with a framebuffer, which is a section of memory that contains 15 a complete frame of data representing pixel values for the display. The LCDC 22 - atmel,at91sam9261-lcdc 23 - atmel,at91sam9263-lcdc [all …]
/linux/Documentation/gpu/
H A D	tegra.rst	2 drm/tegra NVIDIA Tegra GPU and display driver 5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via 6 the host1x controller. host1x supplies command streams, gathered from a push 11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting 18 - A host1x driver that provides infrastructure and access to the host1x 21 - A KMS driver that supports the display controllers as well as a number of 24 - A set of custom userspace IOCTLs that can be used to submit jobs to the 30 The various host1x clients need to be bound together into a logical device in 32 this is implemented in the host1x driver. When a driver is registered with the 33 infrastructure it provides a list of compatible strings specifying the devices [all …]
H A D	komeda-kms.rst	1 .. SPDX-License-Identifier: GPL-2.0 4 drm/komeda Arm display driver 7 The drm/komeda driver supports the Arm display processor D71 and later products, 8 this document gives a brief overview of driver design: how it works and why 11 Overview of D71 like display IPs 14 From D71, Arm display IP begins to adopt a flexible and modularized 15 architecture. A display pipeline is made up of multiple individual and 17 specific capabilities that can give the flowed pipeline pixel data a 23 ----- 30 ------ [all …]
/linux/drivers/auxdisplay/
H A D	line-display.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Character line display core support 30 #include "line-display.h" 35 * linedisp_scroll() - scroll the display by a character 36 * @t: really a pointer to the private data structure 38 * Scroll the current message along the display by one character, rearming the 44 unsigned int i, ch = linedisp->scroll_pos; in linedisp_scroll() 45 unsigned int num_chars = linedisp->num_chars; in linedisp_scroll() 50 for (; i < num_chars && ch < linedisp->message_len; i++, ch++) in linedisp_scroll() 51 linedisp->buf[i] = linedisp->message[ch]; in linedisp_scroll() [all …]
/linux/include/drm/
H A D	gud.h	1 /* SPDX-License-Identifier: MIT / 12 struct gud_display_descriptor_req - Display descriptor 16 * - STATUS_ON_SET: Always do a status request after a SET request. 18 * no way to control the status stage of a control OUT 19 * request that has a payload. 20 * - FULL_UPDATE: Always send the entire framebuffer when flushing changes. 24 * a chance to reset its state machine if needed. 27 * - GUD_COMPRESSION_LZ4: LZ4 lossless compression. 29 * This is useful for devices that don't have a big enough 36 * Devices that have only one display mode will have min_width == max_width [all …]
/linux/Documentation/gpu/amdgpu/display/
H A D	mpo-overview.rst	6 'Documentation/gpu/amdgpu/display/dcn-overview.rst'. 10 fixed-function hardware in the display controller rather than using graphics or 12 the graphics/compute pipelines can be put into low-power states. In summary, 15 * Decreased GPU and CPU workload - no composition shaders needed, no extra 17 * Plane independent page flips - No need to be tied to global compositor 18 page-flip present rate, reduced latency, independent timing. 20 .. note:: Keep in mind that MPO is all about power-saving; if you want to learn 21 more about power-save in the display context, check the link: 22 `Power <https://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rst>`__. 25 model only uses a single userspace IOCTL for configuring the display hardware [all …]
H A D	display-manager.rst	2 AMDgpu Display Manager 8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c [all …]
/linux/Documentation/userspace-api/media/v4l/
H A D	ext-ctrls-colorimetry.rst	1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later 3 .. _colorimetry-controls: 15 ----------------------- 17 .. _colorimetry-control-id: 22 return a description of this control class. 32 .. flat-table:: struct v4l2_ctrl_hdr10_cll_info 33 :header-rows: 0 34 :stub-columns: 0 37 * - __u16 38 - ``max_content_light_level`` [all …]
/linux/tools/perf/Documentation/
H A D	perf-c2c.txt	`1 perf-c2c(1) 5 ---- 6 perf-c2c - Shared Data C2C/HITM Analyzer. 9 -------- 12 'perf c2c record' [<options>] \-- [<record command options>] <command> 16 ----------- 27 required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the 32 - memory address of the access 33 - type of the access (load and store details) 34 - latency (in cycles) of the load access [all …]`
/linux/Documentation/arch/arm/omap/
H A D	dss.rst	`2 OMAP2/3 Display Subsystem 7 TV-out and multiple display support, but there are lots of small improvements 10 The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB, 15 -------- 19 - MIPI DPI (parallel) output 20 - MIPI DSI output in command mode 21 - MIPI DBI (RFBI) output 22 - SDI output 23 - TV output 24 - All pieces can be compiled as a module or inside kernel [all …]`
/linux/Documentation/devicetree/bindings/auxdisplay/
H A D	modtronix,lcd2s.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Modtronix engineering LCD2S Character LCD Display 10 - Lars Poeschel <poeschel@lemonage.de> 13 The LCD2S is a Character LCD Display manufactured by Modtronix Engineering. 14 The display supports a serial I2C and SPI interface. The driver currently 24 I2C bus address of the display. 26 display-height-chars: 27 description: Height of the display, in character cells. [all …]
/linux/include/linux/
H A D	dio.h	1 /* SPDX-License-Identifier: GPL-2.0 / 3 Maybe this should handle DIO-II later? 18 /* The DIO boards in a system are distinguished by 'select codes' which 19 * range from 0-63 (DIO) and 132-255 (DIO-II). 22 * So DIO cards cover [0x600000-0x800000); the areas [0x200000-0x400000) and 23 * [0x800000-0x1000000) are for additional space required by things 24 * like framebuffers. [0x400000-0x600000) is for miscellaneous internal I/O. 27 * DIO-II boards are at 0x1000000 + (sc - 132) * 0x400000 28 * which is address range [0x1000000-0x20000000) -- too big to map completely, 29 * so currently we just don't handle DIO-II boards. It wouldn't be hard to [all …]
/linux/drivers/gpu/drm/vmwgfx/
H A D	vmwgfx_kms.h	1 /* SPDX-License-Identifier: GPL-2.0 OR MIT / 4 Copyright (c) 2009-2025 Broadcom. All Rights Reserved. The term 20 * struct vmw_du_update_plane - Closure structure for vmw_du_helper_plane_update 24 * @du: Display unit on which to update the plane. 25 * @vfb: Framebuffer which is blitted to display unit. 31 * This structure loosely represent the set of operations needed to perform a 32 * plane update on a display unit. Implementer will define that functionality 42 * damage clips on display unit @num_hits will be passed to allocate 54 * like update GB image for proxy surface and define a GMRFB for screen 81 * if needed. This will be called times have damage in display unit, [all …]
/linux/Documentation/admin-guide/laptops/
H A D	asus-laptop.rst	`12 This driver provides support for extra features of ACPI-compatible ASUS laptops. 17 On some models adds support for changing the display brightness and output, 24 ------------ 30 ------ 35 - Fn key combinations 36 - Bluetooth enable and disable 37 - Wlan enable and disable 38 - GPS enable and disable 39 - Video output switching 40 - Ambient Light Sensor on and off [all …]`
/linux/Documentation/devicetree/bindings/display/imx/
H A D	nxp,imx8mq-dcss.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: iMX8MQ Display Controller Subsystem (DCSS) 11 - Laurentiu Palcu <laurentiu.palcu@nxp.com> 15 The DCSS (display controller sub system) is used to source up to three 16 display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP 17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10 18 image processing capabilities are included to provide a solution capable of [all …]
/linux/Documentation/devicetree/bindings/display/sprd/
H A D	sprd,display-subsystem.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Kevin Tang <kevin.tang@unisoc.com> 13 The Unisoc DRM master device is a virtual device needed to list all 14 DPU devices or other display interface nodes that comprise the 17 Unisoc's display pipeline have several components as below description, 18 multi display controllers and corresponding physical interfaces. 19 For different display scenarios, dpu0 and dpu1 maybe binding to different [all …]

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