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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dxilinx.yaml7 title: Xilinx Zynq Platforms
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
23 - digilent,zynq-zybo
24 - digilent,zynq-zybo-z7
26 - myir,zynq-zturn-v5
27 - myir,zynq-zturn
28 - xlnx,zynq-cc108
29 - xlnx,zynq-zc702
30 - xlnx,zynq-zc706
31 - xlnx,zynq-zc770-xm010
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/xilinx/
H A Dxilinx.yaml7 title: Xilinx Zynq Platforms
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
23 - digilent,zynq-zybo
24 - digilent,zynq-zybo-z7
26 - myir,zynq-zturn-v5
27 - myir,zynq-zturn
28 - xlnx,zynq-cc108
29 - xlnx,zynq-zc702
30 - xlnx,zynq-zc706
31 - xlnx,zynq-zc770-xm010
[all …]
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
H A Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
41 For list of all valid reset indices for Zynq UltraScale+ MPSoC see
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dxilinx_can.txt1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
19 - tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN).
20 - rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
29 For Zynq CANPS Dts file:
31 compatible = "xlnx,zynq-can-1.0";
H A Dctu,ctucanfd.yaml16 Integration in Xilinx Zynq SoC based system together with
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
48 for FPGA implementation on Zynq-7000 system).
H A Dxilinx,can.yaml16 - xlnx,zynq-can-1.0
39 description: CAN Tx fifo depth (Zynq, Axi CAN).
43 description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
72 - xlnx,zynq-can-1.0
124 compatible = "xlnx,zynq-can-1.0";
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi9 compatible = "xlnx,zynq-7000";
103 compatible = "xlnx,zynq-xadc-1.00.a";
111 compatible = "xlnx,zynq-can-1.0";
123 compatible = "xlnx,zynq-can-1.0";
135 compatible = "xlnx,zynq-gpio-1.0";
189 compatible = "xlnx,zynq-ddrc-a05";
212 compatible = "xlnx,zynq-spi-r1p6";
224 compatible = "xlnx,zynq-spi-r1p6";
236 compatible = "xlnx,zynq-qspi-1.0";
248 compatible = "xlnx,zynq-gem", "cdns,gem";
[all …]
H A Dzynq-zturn-v5.dts4 /include/ "zynq-zturn-common.dtsi"
7 model = "Zynq Z-Turn MYIR Board V5";
8 compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
H A Dzynq-zturn.dts4 /include/ "zynq-zturn-common.dtsi"
7 model = "Zynq Z-Turn MYIR Board";
8 compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
H A Dzynq-zed.dts7 #include "zynq-7000.dtsi"
11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
H A Dzynq-zybo-z7.dts3 #include "zynq-7000.dtsi"
8 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
29 label = "zynq-zybo-z7:green:ld4";
H A Dzynq-microzed.dts7 /include/ "zynq-7000.dtsi"
11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dxlnx,zynq-ddrc-a05.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
7 title: Zynq A05 DDR Memory Controller
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
H A Dsynopsys.txt6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
23 compatible = "xlnx,zynq-ddrc-a05";
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dxlnx,zynq-qspi.yaml4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
22 const: xlnx,zynq-qspi-1.0
52 compatible = "xlnx,zynq-qspi-1.0";
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
19 (usually 33 MHz oscillators are used for Zynq platforms)
/freebsd/sys/arm/xilinx/
H A Dzy7_gpio.c30 * A GPIO driver for Xilinx Zynq-7000.
32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
36 * Zynq as EMIO signals.
41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
71 /* Zynq 7000 */
103 #define ZYNQ_BANK_NPIN(type, bank) (ZYNQ##type##_BANK##bank##_NPIN)
104 #define ZYNQ_BANK_PIN_MIN(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN)
105 #define ZYNQ_BANK_PIN_MAX(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN + ZYNQ##type##_BANK##bank#…
107 #define ZYNQ_PIN_IS_MIO(type, pin) (pin >= ZYNQ##type##_PIN_MIO_MIN && \
108 pin <= ZYNQ##type##_PIN_MIO_MAX)
[all …]
H A Dzy7_slcr.c30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
78 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
79 "Xilinx Zynq-7000");
83 "Zynq boot mode");
87 "Zynq PSS IDCODE");
91 0, "Zynq REBOOT_STATUS register");
95 0, "Zynq PS_CLK Frequency");
99 0, "Zynq IO PLL Frequency");
103 &arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
[all …]
/freebsd/sys/arm/conf/
H A DZEDBOARD2 # ZEDBOARD -- Custom configuration for the Xilinx Zynq-7000 based
3 # ZedBoard (www.zedboard.org) and similar Zynq boards.
26 makeoptions MODULES_EXTRA="dtb/zynq"
70 device zy7_qspi # Xilinx Zynq QSPI controller
71 device zy7_spi # Xilinx Zynq SPI controller
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-zynq.yaml4 $id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
7 title: Xilinx Zynq GPIO controller
15 - xlnx,zynq-gpio-1.0
63 - xlnx,zynq-gpio-1.0
108 compatible = "xlnx,zynq-gpio-1.0";
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dxilinx-xadc.txt8 frontends for the DRP interface exist. One that is only available on the ZYNQ
9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
88 compatible = "xlnx,zynq-xadc-1.00.a";
/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dxilinx-zynq-fpga-mgr.yaml4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
7 title: Xilinx Zynq FPGA Manager
14 const: xlnx,zynq-devcfg-1.0
46 compatible = "xlnx,zynq-devcfg-1.0";
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dxlnx,zynq-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
7 title: Xilinx Zynq Pinctrl
17 Zynq's pin configuration nodes act as a container for an arbitrary number of
31 const: xlnx,zynq-pinctrl
182 #include <dt-bindings/pinctrl/pinctrl-zynq.h>
184 compatible = "xlnx,zynq-pinctrl";
H A Dxlnx,pinctrl-zynq.yaml4 $id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml#
7 title: Xilinx Zynq Pinctrl
17 Zynq's pin configuration nodes act as a container for an arbitrary number of
31 const: xlnx,pinctrl-zynq
182 #include <dt-bindings/pinctrl/pinctrl-zynq.h>
184 compatible = "xlnx,pinctrl-zynq";

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