| /freebsd/sys/contrib/device-tree/src/riscv/sophgo/ |
| H A D | sg2044-cpus.dtsi | 33 "zbs", "zca", "zcb", "zcd",
69 "zbs", "zca", "zcb", "zcd",
105 "zbs", "zca", "zcb", "zcd",
141 "zbs", "zca", "zcb", "zcd",
177 "zbs", "zca", "zcb", "zcd",
213 "zbs", "zca", "zcb", "zcd",
249 "zbs", "zca", "zcb", "zcd",
285 "zbs", "zca", "zcb", "zcd",
321 "zbs", "zca", "zcb", "zcd",
357 "zbs", "zca", "zcb", "zcd",
[all …]
|
| /freebsd/secure/lib/libcrypto/man/man3/ |
| H A D | OPENSSL_riscvcap.3 | 94 zba/zbb/zbs would not be implied in the capability vector.
112 .IP ZBS 4
113 .IX Item "ZBS"
|
| /freebsd/sys/contrib/device-tree/src/riscv/spacemit/ |
| H A D | k1.dtsi | 61 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
91 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
121 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
151 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
181 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
211 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
241 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
271 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
| /freebsd/crypto/openssl/doc/man3/ |
| H A D | OPENSSL_riscvcap.pod | 33 zba/zbb/zbs would not be implied in the capability vector.
57 =item ZBS
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVScheduleZb.td | 33 // Zbs extension
72 // Zbs extension
|
| H A D | RISCVSchedXiangShanNanHu.td | 97 // Zbs
296 // Zbs
|
| H A D | RISCVFeatures.td | 498 : RISCVExtension<"zbs", 1, 0,
499 "'Zbs' (Single-Bit Instructions)">,
503 "'Zbs' (Single-Bit Instructions)">;
509 "'B' (the collection of the Zba, Zbb, Zbs extensions)",
513 "'B' (the collection of the Zba, Zbb, Zbs extensions)">;
|
| H A D | RISCVInstrInfoZb.td | 14 // Zbs - 1.0
|
| H A D | RISCVISelLowering.cpp | 1948 // We expect to be able to match a bit extraction instruction if the Zbs in isMaskAndCmp0FoldingBeneficial()
1974 // Zbs provides BEXT[_I], which can be used with SEQZ/SNEZ as a bit test. in hasBitTest()
13670 // Pre-promote (i1 (truncate (srl X, Y))) on RV64 with Zbs without zero in performTRUNCATECombine()
13697 // Pre-promote (i32 (and (srl X, Y), 1)) on RV64 with Zbs without zero in performANDCombine()
13797 // Pre-promote (i32 (xor (shl -1, X), ~0)) on RV64 with Zbs so we can use in performXORCombine()
|
| /freebsd/crypto/openssl/include/crypto/ |
| H A D | riscv_arch.def | 32 RISCV_DEFINE_CAP(ZBS, 0, 3, 4, (1 << 5))
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 315 // Perform optimization with BSETI in the Zbs extension. in generateInstSeq()
336 // Perform optimization with BCLRI in the Zbs extension. in generateInstSeq()
|
| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | extensions.yaml | 295 - const: zbs
297 The standard Zbs bit-manipulation extension for single-bit
|
| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | Host.cpp | 2069 Features["zbs"] = ExtMask & (1 << 5); // RISCV_HWPROBE_EXT_ZBS in getHostCPUFeatures()
|