xref: /freebsd/sys/contrib/device-tree/src/riscv/sophgo/sg2044-cpus.dtsi (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa)

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
 */

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <50000000>;

		cpu0: cpu@0 {
			compatible = "thead,c920", "riscv";
			reg = <0>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache0>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu1: cpu@1 {
			compatible = "thead,c920", "riscv";
			reg = <1>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache0>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu2: cpu@2 {
			compatible = "thead,c920", "riscv";
			reg = <2>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache0>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu3: cpu@3 {
			compatible = "thead,c920", "riscv";
			reg = <3>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache0>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu3_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu4: cpu@4 {
			compatible = "thead,c920", "riscv";
			reg = <4>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache1>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu4_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu5: cpu@5 {
			compatible = "thead,c920", "riscv";
			reg = <5>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache1>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu5_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu6: cpu@6 {
			compatible = "thead,c920", "riscv";
			reg = <6>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache1>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu6_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu7: cpu@7 {
			compatible = "thead,c920", "riscv";
			reg = <7>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache1>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu7_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu8: cpu@8 {
			compatible = "thead,c920", "riscv";
			reg = <8>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache2>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu8_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu9: cpu@9 {
			compatible = "thead,c920", "riscv";
			reg = <9>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache2>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu9_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu10: cpu@10 {
			compatible = "thead,c920", "riscv";
			reg = <10>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache2>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu10_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu11: cpu@11 {
			compatible = "thead,c920", "riscv";
			reg = <11>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache2>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu11_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu12: cpu@12 {
			compatible = "thead,c920", "riscv";
			reg = <12>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache3>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu12_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu13: cpu@13 {
			compatible = "thead,c920", "riscv";
			reg = <13>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache3>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu13_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu14: cpu@14 {
			compatible = "thead,c920", "riscv";
			reg = <14>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache3>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu14_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu15: cpu@15 {
			compatible = "thead,c920", "riscv";
			reg = <15>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache3>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu15_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu16: cpu@16 {
			compatible = "thead,c920", "riscv";
			reg = <16>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache4>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu16_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu17: cpu@17 {
			compatible = "thead,c920", "riscv";
			reg = <17>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache4>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu17_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu18: cpu@18 {
			compatible = "thead,c920", "riscv";
			reg = <18>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache4>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu18_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu19: cpu@19 {
			compatible = "thead,c920", "riscv";
			reg = <19>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache4>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu19_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu20: cpu@20 {
			compatible = "thead,c920", "riscv";
			reg = <20>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache5>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu20_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu21: cpu@21 {
			compatible = "thead,c920", "riscv";
			reg = <21>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache5>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu21_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu22: cpu@22 {
			compatible = "thead,c920", "riscv";
			reg = <22>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache5>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu22_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu23: cpu@23 {
			compatible = "thead,c920", "riscv";
			reg = <23>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache5>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu23_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu24: cpu@24 {
			compatible = "thead,c920", "riscv";
			reg = <24>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache6>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu24_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu25: cpu@25 {
			compatible = "thead,c920", "riscv";
			reg = <25>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache6>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu25_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu26: cpu@26 {
			compatible = "thead,c920", "riscv";
			reg = <26>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache6>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu26_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu27: cpu@27 {
			compatible = "thead,c920", "riscv";
			reg = <27>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache6>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu27_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu28: cpu@28 {
			compatible = "thead,c920", "riscv";
			reg = <28>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache7>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu28_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu29: cpu@29 {
			compatible = "thead,c920", "riscv";
			reg = <29>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache7>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu29_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu30: cpu@30 {
			compatible = "thead,c920", "riscv";
			reg = <30>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache7>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu30_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu31: cpu@31 {
			compatible = "thead,c920", "riscv";
			reg = <31>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache7>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu31_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu32: cpu@32 {
			compatible = "thead,c920", "riscv";
			reg = <32>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache8>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu32_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu33: cpu@33 {
			compatible = "thead,c920", "riscv";
			reg = <33>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache8>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu33_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu34: cpu@34 {
			compatible = "thead,c920", "riscv";
			reg = <34>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache8>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu34_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu35: cpu@35 {
			compatible = "thead,c920", "riscv";
			reg = <35>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache8>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu35_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu36: cpu@36 {
			compatible = "thead,c920", "riscv";
			reg = <36>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache9>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu36_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu37: cpu@37 {
			compatible = "thead,c920", "riscv";
			reg = <37>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache9>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu37_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu38: cpu@38 {
			compatible = "thead,c920", "riscv";
			reg = <38>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache9>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu38_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu39: cpu@39 {
			compatible = "thead,c920", "riscv";
			reg = <39>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache9>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu39_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu40: cpu@40 {
			compatible = "thead,c920", "riscv";
			reg = <40>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache10>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu40_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu41: cpu@41 {
			compatible = "thead,c920", "riscv";
			reg = <41>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache10>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu41_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu42: cpu@42 {
			compatible = "thead,c920", "riscv";
			reg = <42>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache10>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu42_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu43: cpu@43 {
			compatible = "thead,c920", "riscv";
			reg = <43>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache10>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu43_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu44: cpu@44 {
			compatible = "thead,c920", "riscv";
			reg = <44>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache11>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu44_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu45: cpu@45 {
			compatible = "thead,c920", "riscv";
			reg = <45>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache11>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu45_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu46: cpu@46 {
			compatible = "thead,c920", "riscv";
			reg = <46>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache11>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu46_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu47: cpu@47 {
			compatible = "thead,c920", "riscv";
			reg = <47>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache11>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu47_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu48: cpu@48 {
			compatible = "thead,c920", "riscv";
			reg = <48>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache12>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu48_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu49: cpu@49 {
			compatible = "thead,c920", "riscv";
			reg = <49>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache12>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu49_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu50: cpu@50 {
			compatible = "thead,c920", "riscv";
			reg = <50>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache12>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu50_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu51: cpu@51 {
			compatible = "thead,c920", "riscv";
			reg = <51>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache12>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu51_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu52: cpu@52 {
			compatible = "thead,c920", "riscv";
			reg = <52>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache13>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu52_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu53: cpu@53 {
			compatible = "thead,c920", "riscv";
			reg = <53>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache13>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu53_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu54: cpu@54 {
			compatible = "thead,c920", "riscv";
			reg = <54>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache13>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu54_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu55: cpu@55 {
			compatible = "thead,c920", "riscv";
			reg = <55>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache13>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu55_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu56: cpu@56 {
			compatible = "thead,c920", "riscv";
			reg = <56>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache14>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu56_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu57: cpu@57 {
			compatible = "thead,c920", "riscv";
			reg = <57>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache14>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu57_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu58: cpu@58 {
			compatible = "thead,c920", "riscv";
			reg = <58>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache14>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu58_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu59: cpu@59 {
			compatible = "thead,c920", "riscv";
			reg = <59>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache14>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu59_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu60: cpu@60 {
			compatible = "thead,c920", "riscv";
			reg = <60>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache15>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu60_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu61: cpu@61 {
			compatible = "thead,c920", "riscv";
			reg = <61>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache15>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu61_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu62: cpu@62 {
			compatible = "thead,c920", "riscv";
			reg = <62>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache15>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu62_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu63: cpu@63 {
			compatible = "thead,c920", "riscv";
			reg = <63>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache15>;
			riscv,isa = "rv64imafdcv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu63_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu-map {
			socket0 {
				cluster0 {
					core0 {
						cpu = <&cpu0>;
					};

					core1 {
						cpu = <&cpu1>;
					};

					core2 {
						cpu = <&cpu2>;
					};

					core3 {
						cpu = <&cpu3>;
					};
				};

				cluster1 {
					core0 {
						cpu = <&cpu4>;
					};

					core1 {
						cpu = <&cpu5>;
					};

					core2 {
						cpu = <&cpu6>;
					};

					core3 {
						cpu = <&cpu7>;
					};
				};

				cluster2 {
					core0 {
						cpu = <&cpu8>;
					};

					core1 {
						cpu = <&cpu9>;
					};

					core2 {
						cpu = <&cpu10>;
					};

					core3 {
						cpu = <&cpu11>;
					};
				};

				cluster3 {
					core0 {
						cpu = <&cpu12>;
					};

					core1 {
						cpu = <&cpu13>;
					};

					core2 {
						cpu = <&cpu14>;
					};

					core3 {
						cpu = <&cpu15>;
					};
				};

				cluster4 {
					core0 {
						cpu = <&cpu16>;
					};

					core1 {
						cpu = <&cpu17>;
					};

					core2 {
						cpu = <&cpu18>;
					};

					core3 {
						cpu = <&cpu19>;
					};
				};

				cluster5 {
					core0 {
						cpu = <&cpu20>;
					};

					core1 {
						cpu = <&cpu21>;
					};

					core2 {
						cpu = <&cpu22>;
					};

					core3 {
						cpu = <&cpu23>;
					};
				};

				cluster6 {
					core0 {
						cpu = <&cpu24>;
					};

					core1 {
						cpu = <&cpu25>;
					};

					core2 {
						cpu = <&cpu26>;
					};

					core3 {
						cpu = <&cpu27>;
					};
				};

				cluster7 {
					core0 {
						cpu = <&cpu28>;
					};

					core1 {
						cpu = <&cpu29>;
					};

					core2 {
						cpu = <&cpu30>;
					};

					core3 {
						cpu = <&cpu31>;
					};
				};

				cluster8 {
					core0 {
						cpu = <&cpu32>;
					};

					core1 {
						cpu = <&cpu33>;
					};

					core2 {
						cpu = <&cpu34>;
					};

					core3 {
						cpu = <&cpu35>;
					};
				};

				cluster9 {
					core0 {
						cpu = <&cpu36>;
					};

					core1 {
						cpu = <&cpu37>;
					};

					core2 {
						cpu = <&cpu38>;
					};

					core3 {
						cpu = <&cpu39>;
					};
				};

				cluster10 {
					core0 {
						cpu = <&cpu40>;
					};

					core1 {
						cpu = <&cpu41>;
					};

					core2 {
						cpu = <&cpu42>;
					};

					core3 {
						cpu = <&cpu43>;
					};
				};

				cluster11 {
					core0 {
						cpu = <&cpu44>;
					};

					core1 {
						cpu = <&cpu45>;
					};

					core2 {
						cpu = <&cpu46>;
					};

					core3 {
						cpu = <&cpu47>;
					};
				};

				cluster12 {
					core0 {
						cpu = <&cpu48>;
					};

					core1 {
						cpu = <&cpu49>;
					};

					core2 {
						cpu = <&cpu50>;
					};

					core3 {
						cpu = <&cpu51>;
					};
				};

				cluster13 {
					core0 {
						cpu = <&cpu52>;
					};

					core1 {
						cpu = <&cpu53>;
					};

					core2 {
						cpu = <&cpu54>;
					};

					core3 {
						cpu = <&cpu55>;
					};
				};

				cluster14 {
					core0 {
						cpu = <&cpu56>;
					};

					core1 {
						cpu = <&cpu57>;
					};

					core2 {
						cpu = <&cpu58>;
					};

					core3 {
						cpu = <&cpu59>;
					};
				};

				cluster15 {
					core0 {
						cpu = <&cpu60>;
					};

					core1 {
						cpu = <&cpu61>;
					};

					core2 {
						cpu = <&cpu62>;
					};

					core3 {
						cpu = <&cpu63>;
					};
				};
			};
		};

		l2_cache0: cache-controller-0 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache1: cache-controller-1 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache2: cache-controller-2 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache3: cache-controller-3 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache4: cache-controller-4 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache5: cache-controller-5 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache6: cache-controller-6 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache7: cache-controller-7 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache8: cache-controller-8 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache9: cache-controller-9 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache10: cache-controller-10 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache11: cache-controller-11 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache12: cache-controller-12 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache13: cache-controller-13 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache14: cache-controller-14 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache15: cache-controller-15 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <2097152>;
			cache-sets = <2048>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l3_cache: cache-controller-16 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <3>;
			cache-size = <67108864>;
			cache-sets = <4096>;
			cache-unified;
		};
	};

	pmu {
		compatible = "riscv,pmu";
		riscv,event-to-mhpmevent =
			<0x00003 0x00000000 0x00000010>,
			<0x00004 0x00000000 0x00000011>,
			<0x00005 0x00000000 0x00000007>,
			<0x00006 0x00000000 0x00000006>,
			<0x00008 0x00000000 0x00000027>,
			<0x00009 0x00000000 0x00000028>,
			<0x10000 0x00000000 0x0000000c>,
			<0x10001 0x00000000 0x0000000d>,
			<0x10002 0x00000000 0x0000000e>,
			<0x10003 0x00000000 0x0000000f>,
			<0x10008 0x00000000 0x00000001>,
			<0x10009 0x00000000 0x00000002>,
			<0x10010 0x00000000 0x00000010>,
			<0x10011 0x00000000 0x00000011>,
			<0x10012 0x00000000 0x00000012>,
			<0x10013 0x00000000 0x00000013>,
			<0x10019 0x00000000 0x00000004>,
			<0x10021 0x00000000 0x00000003>,
			<0x10030 0x00000000 0x0000001c>,
			<0x10031 0x00000000 0x0000001b>;
		riscv,event-to-mhpmcounters =
			<0x00003 0x00003 0xfffffff8>,
			<0x00004 0x00004 0xfffffff8>,
			<0x00005 0x00005 0xfffffff8>,
			<0x00006 0x00006 0xfffffff8>,
			<0x00007 0x00007 0xfffffff8>,
			<0x00008 0x00008 0xfffffff8>,
			<0x00009 0x00009 0xfffffff8>,
			<0x0000a 0x0000a 0xfffffff8>,
			<0x10000 0x10000 0xfffffff8>,
			<0x10001 0x10001 0xfffffff8>,
			<0x10002 0x10002 0xfffffff8>,
			<0x10003 0x10003 0xfffffff8>,
			<0x10008 0x10008 0xfffffff8>,
			<0x10009 0x10009 0xfffffff8>,
			<0x10010 0x10010 0xfffffff8>,
			<0x10011 0x10011 0xfffffff8>,
			<0x10012 0x10012 0xfffffff8>,
			<0x10013 0x10013 0xfffffff8>,
			<0x10019 0x10019 0xfffffff8>,
			<0x10021 0x10021 0xfffffff8>,
			<0x10030 0x10030 0xfffffff8>,
			<0x10031 0x10031 0xfffffff8>;
		riscv,raw-event-to-mhpmcounters =
			<0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
			<0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
	};

	soc {
		intc: interrupt-controller@6d40000000 {
			compatible = "sophgo,sg2044-plic", "thead,c900-plic";
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x6d 0x40000000 0x0 0x4000000>;
			interrupt-controller;
			interrupts-extended =
				<&cpu0_intc 11>, <&cpu0_intc 9>,
				<&cpu1_intc 11>, <&cpu1_intc 9>,
				<&cpu2_intc 11>, <&cpu2_intc 9>,
				<&cpu3_intc 11>, <&cpu3_intc 9>,
				<&cpu4_intc 11>, <&cpu4_intc 9>,
				<&cpu5_intc 11>, <&cpu5_intc 9>,
				<&cpu6_intc 11>, <&cpu6_intc 9>,
				<&cpu7_intc 11>, <&cpu7_intc 9>,
				<&cpu8_intc 11>, <&cpu8_intc 9>,
				<&cpu9_intc 11>, <&cpu9_intc 9>,
				<&cpu10_intc 11>, <&cpu10_intc 9>,
				<&cpu11_intc 11>, <&cpu11_intc 9>,
				<&cpu12_intc 11>, <&cpu12_intc 9>,
				<&cpu13_intc 11>, <&cpu13_intc 9>,
				<&cpu14_intc 11>, <&cpu14_intc 9>,
				<&cpu15_intc 11>, <&cpu15_intc 9>,
				<&cpu16_intc 11>, <&cpu16_intc 9>,
				<&cpu17_intc 11>, <&cpu17_intc 9>,
				<&cpu18_intc 11>, <&cpu18_intc 9>,
				<&cpu19_intc 11>, <&cpu19_intc 9>,
				<&cpu20_intc 11>, <&cpu20_intc 9>,
				<&cpu21_intc 11>, <&cpu21_intc 9>,
				<&cpu22_intc 11>, <&cpu22_intc 9>,
				<&cpu23_intc 11>, <&cpu23_intc 9>,
				<&cpu24_intc 11>, <&cpu24_intc 9>,
				<&cpu25_intc 11>, <&cpu25_intc 9>,
				<&cpu26_intc 11>, <&cpu26_intc 9>,
				<&cpu27_intc 11>, <&cpu27_intc 9>,
				<&cpu28_intc 11>, <&cpu28_intc 9>,
				<&cpu29_intc 11>, <&cpu29_intc 9>,
				<&cpu30_intc 11>, <&cpu30_intc 9>,
				<&cpu31_intc 11>, <&cpu31_intc 9>,
				<&cpu32_intc 11>, <&cpu32_intc 9>,
				<&cpu33_intc 11>, <&cpu33_intc 9>,
				<&cpu34_intc 11>, <&cpu34_intc 9>,
				<&cpu35_intc 11>, <&cpu35_intc 9>,
				<&cpu36_intc 11>, <&cpu36_intc 9>,
				<&cpu37_intc 11>, <&cpu37_intc 9>,
				<&cpu38_intc 11>, <&cpu38_intc 9>,
				<&cpu39_intc 11>, <&cpu39_intc 9>,
				<&cpu40_intc 11>, <&cpu40_intc 9>,
				<&cpu41_intc 11>, <&cpu41_intc 9>,
				<&cpu42_intc 11>, <&cpu42_intc 9>,
				<&cpu43_intc 11>, <&cpu43_intc 9>,
				<&cpu44_intc 11>, <&cpu44_intc 9>,
				<&cpu45_intc 11>, <&cpu45_intc 9>,
				<&cpu46_intc 11>, <&cpu46_intc 9>,
				<&cpu47_intc 11>, <&cpu47_intc 9>,
				<&cpu48_intc 11>, <&cpu48_intc 9>,
				<&cpu49_intc 11>, <&cpu49_intc 9>,
				<&cpu50_intc 11>, <&cpu50_intc 9>,
				<&cpu51_intc 11>, <&cpu51_intc 9>,
				<&cpu52_intc 11>, <&cpu52_intc 9>,
				<&cpu53_intc 11>, <&cpu53_intc 9>,
				<&cpu54_intc 11>, <&cpu54_intc 9>,
				<&cpu55_intc 11>, <&cpu55_intc 9>,
				<&cpu56_intc 11>, <&cpu56_intc 9>,
				<&cpu57_intc 11>, <&cpu57_intc 9>,
				<&cpu58_intc 11>, <&cpu58_intc 9>,
				<&cpu59_intc 11>, <&cpu59_intc 9>,
				<&cpu60_intc 11>, <&cpu60_intc 9>,
				<&cpu61_intc 11>, <&cpu61_intc 9>,
				<&cpu62_intc 11>, <&cpu62_intc 9>,
				<&cpu63_intc 11>, <&cpu63_intc 9>;
			riscv,ndev = <863>;
		};

		aclint_mswi: interrupt-controller@6d44000000 {
			compatible = "sophgo,sg2044-aclint-mswi", "thead,c900-aclint-mswi";
			reg = <0x6d 0x44000000 0x0 0x4000>;
			interrupts-extended = <&cpu0_intc 3>,
					      <&cpu1_intc 3>,
					      <&cpu2_intc 3>,
					      <&cpu3_intc 3>,
					      <&cpu4_intc 3>,
					      <&cpu5_intc 3>,
					      <&cpu6_intc 3>,
					      <&cpu7_intc 3>,
					      <&cpu8_intc 3>,
					      <&cpu9_intc 3>,
					      <&cpu10_intc 3>,
					      <&cpu11_intc 3>,
					      <&cpu12_intc 3>,
					      <&cpu13_intc 3>,
					      <&cpu14_intc 3>,
					      <&cpu15_intc 3>,
					      <&cpu16_intc 3>,
					      <&cpu17_intc 3>,
					      <&cpu18_intc 3>,
					      <&cpu19_intc 3>,
					      <&cpu20_intc 3>,
					      <&cpu21_intc 3>,
					      <&cpu22_intc 3>,
					      <&cpu23_intc 3>,
					      <&cpu24_intc 3>,
					      <&cpu25_intc 3>,
					      <&cpu26_intc 3>,
					      <&cpu27_intc 3>,
					      <&cpu28_intc 3>,
					      <&cpu29_intc 3>,
					      <&cpu30_intc 3>,
					      <&cpu31_intc 3>,
					      <&cpu32_intc 3>,
					      <&cpu33_intc 3>,
					      <&cpu34_intc 3>,
					      <&cpu35_intc 3>,
					      <&cpu36_intc 3>,
					      <&cpu37_intc 3>,
					      <&cpu38_intc 3>,
					      <&cpu39_intc 3>,
					      <&cpu40_intc 3>,
					      <&cpu41_intc 3>,
					      <&cpu42_intc 3>,
					      <&cpu43_intc 3>,
					      <&cpu44_intc 3>,
					      <&cpu45_intc 3>,
					      <&cpu46_intc 3>,
					      <&cpu47_intc 3>,
					      <&cpu48_intc 3>,
					      <&cpu49_intc 3>,
					      <&cpu50_intc 3>,
					      <&cpu51_intc 3>,
					      <&cpu52_intc 3>,
					      <&cpu53_intc 3>,
					      <&cpu54_intc 3>,
					      <&cpu55_intc 3>,
					      <&cpu56_intc 3>,
					      <&cpu57_intc 3>,
					      <&cpu58_intc 3>,
					      <&cpu59_intc 3>,
					      <&cpu60_intc 3>,
					      <&cpu61_intc 3>,
					      <&cpu62_intc 3>,
					      <&cpu63_intc 3>;
		};

		aclint_mtimer: timer@6d44004000 {
			compatible = "sophgo,sg2044-aclint-mtimer", "thead,c900-aclint-mtimer";
			reg = <0x6d 0x44004000 0x0 0x8000>;
			reg-names = "mtimecmp";
			interrupts-extended = <&cpu0_intc 7>,
					      <&cpu1_intc 7>,
					      <&cpu2_intc 7>,
					      <&cpu3_intc 7>,
					      <&cpu4_intc 7>,
					      <&cpu5_intc 7>,
					      <&cpu6_intc 7>,
					      <&cpu7_intc 7>,
					      <&cpu8_intc 7>,
					      <&cpu9_intc 7>,
					      <&cpu10_intc 7>,
					      <&cpu11_intc 7>,
					      <&cpu12_intc 7>,
					      <&cpu13_intc 7>,
					      <&cpu14_intc 7>,
					      <&cpu15_intc 7>,
					      <&cpu16_intc 7>,
					      <&cpu17_intc 7>,
					      <&cpu18_intc 7>,
					      <&cpu19_intc 7>,
					      <&cpu20_intc 7>,
					      <&cpu21_intc 7>,
					      <&cpu22_intc 7>,
					      <&cpu23_intc 7>,
					      <&cpu24_intc 7>,
					      <&cpu25_intc 7>,
					      <&cpu26_intc 7>,
					      <&cpu27_intc 7>,
					      <&cpu28_intc 7>,
					      <&cpu29_intc 7>,
					      <&cpu30_intc 7>,
					      <&cpu31_intc 7>,
					      <&cpu32_intc 7>,
					      <&cpu33_intc 7>,
					      <&cpu34_intc 7>,
					      <&cpu35_intc 7>,
					      <&cpu36_intc 7>,
					      <&cpu37_intc 7>,
					      <&cpu38_intc 7>,
					      <&cpu39_intc 7>,
					      <&cpu40_intc 7>,
					      <&cpu41_intc 7>,
					      <&cpu42_intc 7>,
					      <&cpu43_intc 7>,
					      <&cpu44_intc 7>,
					      <&cpu45_intc 7>,
					      <&cpu46_intc 7>,
					      <&cpu47_intc 7>,
					      <&cpu48_intc 7>,
					      <&cpu49_intc 7>,
					      <&cpu50_intc 7>,
					      <&cpu51_intc 7>,
					      <&cpu52_intc 7>,
					      <&cpu53_intc 7>,
					      <&cpu54_intc 7>,
					      <&cpu55_intc 7>,
					      <&cpu56_intc 7>,
					      <&cpu57_intc 7>,
					      <&cpu58_intc 7>,
					      <&cpu59_intc 7>,
					      <&cpu60_intc 7>,
					      <&cpu61_intc 7>,
					      <&cpu62_intc 7>,
					      <&cpu63_intc 7>;
		};

		aclint_sswi: interrupt-controller@6d4400c000 {
			compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
			reg = <0x6d 0x4400c000 0x0 0x1000>;
			#interrupt-cells = <0>;
			interrupt-controller;
			interrupts-extended = <&cpu0_intc 1>,
					      <&cpu1_intc 1>,
					      <&cpu2_intc 1>,
					      <&cpu3_intc 1>,
					      <&cpu4_intc 1>,
					      <&cpu5_intc 1>,
					      <&cpu6_intc 1>,
					      <&cpu7_intc 1>,
					      <&cpu8_intc 1>,
					      <&cpu9_intc 1>,
					      <&cpu10_intc 1>,
					      <&cpu11_intc 1>,
					      <&cpu12_intc 1>,
					      <&cpu13_intc 1>,
					      <&cpu14_intc 1>,
					      <&cpu15_intc 1>,
					      <&cpu16_intc 1>,
					      <&cpu17_intc 1>,
					      <&cpu18_intc 1>,
					      <&cpu19_intc 1>,
					      <&cpu20_intc 1>,
					      <&cpu21_intc 1>,
					      <&cpu22_intc 1>,
					      <&cpu23_intc 1>,
					      <&cpu24_intc 1>,
					      <&cpu25_intc 1>,
					      <&cpu26_intc 1>,
					      <&cpu27_intc 1>,
					      <&cpu28_intc 1>,
					      <&cpu29_intc 1>,
					      <&cpu30_intc 1>,
					      <&cpu31_intc 1>,
					      <&cpu32_intc 1>,
					      <&cpu33_intc 1>,
					      <&cpu34_intc 1>,
					      <&cpu35_intc 1>,
					      <&cpu36_intc 1>,
					      <&cpu37_intc 1>,
					      <&cpu38_intc 1>,
					      <&cpu39_intc 1>,
					      <&cpu40_intc 1>,
					      <&cpu41_intc 1>,
					      <&cpu42_intc 1>,
					      <&cpu43_intc 1>,
					      <&cpu44_intc 1>,
					      <&cpu45_intc 1>,
					      <&cpu46_intc 1>,
					      <&cpu47_intc 1>,
					      <&cpu48_intc 1>,
					      <&cpu49_intc 1>,
					      <&cpu50_intc 1>,
					      <&cpu51_intc 1>,
					      <&cpu52_intc 1>,
					      <&cpu53_intc 1>,
					      <&cpu54_intc 1>,
					      <&cpu55_intc 1>,
					      <&cpu56_intc 1>,
					      <&cpu57_intc 1>,
					      <&cpu58_intc 1>,
					      <&cpu59_intc 1>,
					      <&cpu60_intc 1>,
					      <&cpu61_intc 1>,
					      <&cpu62_intc 1>,
					      <&cpu63_intc 1>;
		};
	};
};