/linux/Documentation/devicetree/bindings/clock/ |
H A D | armada3700-xtal-clock.txt | 1 * Xtal Clock bindings for Marvell Armada 37xx SoCs 3 Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by 12 "marvell,armada-3700-xtal-clock" 17 output names ("xtal") 24 xtalclk: xtal-clk { 25 compatible = "marvell,armada-3700-xtal-clock"; 26 clock-output-names = "xtal";
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H A D | silabs,si5351.yaml | 50 - const: xtal 62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). 106 2 - use XTAL for this output 212 /* Connect XTAL input to 25MHz reference */ 214 clock-names = "xtal"; 216 /* Use XTAL input as source of PLL0 and PLL1 */ 258 * - XTAL as clock source of output divider
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H A D | marvell,armada-3700-uart-clock.yaml | 23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal" 28 used for UART (most probably xtal) for smooth boot log on UART. 36 - const: xtal 57 clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
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H A D | amlogic,s4-pll-clkc.yaml | 25 - const: xtal 44 clocks = <&xtal>; 45 clock-names = "xtal";
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H A D | amlogic,meson8-ddr-clkc.yaml | 26 - const: xtal 45 clocks = <&xtal>; 46 clock-names = "xtal";
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H A D | nxp,lpc3220-clk.yaml | 32 - const: xtal 49 clocks = <&xtal_32k>, <&xtal>; 50 clock-names = "xtal_32k", "xtal";
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H A D | lpc1850-cgu.txt | 33 order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin. 81 xtal: xtal { 120 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
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H A D | amlogic,a1-peripherals-clkc.yaml | 43 - const: xtal 72 <&xtal>, 76 "hifi_pll", "xtal", "sys_pll";
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/linux/arch/arm64/boot/dts/amlogic/ |
H A D | amlogic-t7-a311d2-an400.dts | 27 xtal: xtal-clk { label 30 clock-output-names = "xtal"; 36 clocks = <&xtal>, <&xtal>, <&xtal>; 37 clock-names = "xtal", "pclk", "baud";
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H A D | amlogic-t7-a311d2-khadas-vim4.dts | 41 xtal: xtal-clk { label 44 clock-output-names = "xtal"; 52 clocks = <&xtal>, <&xtal>, <&xtal>; 53 clock-names = "xtal", "pclk", "baud";
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H A D | amlogic-a4-common.dtsi | 23 xtal: xtal-clk { label 26 clock-output-names = "xtal"; 58 clocks = <&xtal>; 66 clocks = <&xtal>, <&xtal>, <&xtal>; 67 clock-names = "xtal", "pclk", "baud";
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H A D | meson-gxbb.dtsi | 286 clocks = <&xtal>, <&clkc CLKID_CLK81>; 287 clock-names = "xtal", "mpeg-clk"; 322 assigned-clock-parents = <&xtal>, <0>; 330 clocks = <&xtal>; 331 clock-names = "xtal"; 789 clocks = <&xtal>, 838 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 839 clock-names = "xtal", "pclk", "baud"; 843 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 844 clock-names = "xtal", "pclk", "baud"; [all …]
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H A D | meson-gxl.dtsi | 310 clocks = <&xtal>, <&clkc CLKID_CLK81>; 311 clock-names = "xtal", "mpeg-clk"; 334 assigned-clock-parents = <&xtal>, <0>; 342 clocks = <&xtal>; 343 clock-names = "xtal"; 859 clocks = <&xtal>, 908 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 909 clock-names = "xtal", "pclk", "baud"; 913 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 914 clock-names = "xtal", "pclk", "baud"; [all …]
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H A D | meson-s4.dtsi | 62 xtal: xtal-clk { label 65 clock-output-names = "xtal"; 121 <&xtal>; 125 "mpll2", "mpll3", "hdmi_pll", "xtal"; 132 clocks = <&xtal>; 133 clock-names = "xtal"; 140 clocks = <&xtal>; 606 <&xtal>, 755 clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>; 756 clock-names = "xtal", "pclk", "baud"; [all …]
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H A D | meson-axg.dtsi | 1251 clocks = <&xtal>; 1252 clock-names = "xtal"; 1575 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1576 clock-names = "xtal", "mpeg-clk"; 1706 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1707 clock-names = "xtal", "pclk", "baud"; 1715 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1716 clock-names = "xtal", "pclk", "baud"; 1750 clocks = <&xtal>, 1805 clocks = <&xtal>; [all …]
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/linux/drivers/clk/pistachio/ |
H A D | clk-pistachio.c | 70 DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10), 105 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" }; 106 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" }; 107 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" }; 109 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" }; 110 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" }; 112 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" }; 113 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" }; 114 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" }; 117 PNAME(mux_xtal_sys) = { "xtal", "sys_pll" }; [all …]
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/linux/drivers/media/pci/cx18/ |
H A D | cx18-av-audio.c | 66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq() 70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq() 74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq() 101 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq() 105 /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/ in set_audclk_freq() 109 /* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */ in set_audclk_freq() 136 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq() 140 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/ in set_audclk_freq() 144 /* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */ in set_audclk_freq() 173 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq() [all …]
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/linux/drivers/clk/renesas/ |
H A D | rcar-usb2-clock-sel.c | 40 bool xtal; member 49 priv->extal, priv->xtal, val); in usb2_clock_sel_enable_extal_only() 51 if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) in usb2_clock_sel_enable_extal_only() 57 if (priv->extal && !priv->xtal) in usb2_clock_sel_disable_extal_only() 169 priv->xtal = !!clk_get_rate(clk); in rcar_usb2_clock_sel_probe() 173 if (!priv->extal && !priv->xtal) { in rcar_usb2_clock_sel_probe()
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/linux/drivers/phy/ralink/ |
H A D | phy-mt7621-pci.c | 70 * @sys_clk: pointer to the system XTAL clock 127 /* Debug Xtal Type */ in mt7621_set_phy_for_ssc() 142 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc() 147 dev_dbg(dev, "Xtal is 40MHz\n"); in mt7621_set_phy_for_ssc() 174 dev_dbg(dev, "Xtal is 25MHz\n"); in mt7621_set_phy_for_ssc() 175 } else { /* 20MHz Xtal */ in mt7621_set_phy_for_ssc() 179 dev_dbg(dev, "Xtal is 20MHz\n"); in mt7621_set_phy_for_ssc() 199 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
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/linux/drivers/clk/mvebu/ |
H A D | armada-37xx-xtal.c | 3 * Marvell Armada 37xx SoC xtal clocks 22 const char *xtal_name = "xtal"; in armada_3700_xtal_clock_probe() 74 { .compatible = "marvell,armada-3700-xtal-clock", }, 82 .name = "marvell-armada-3700-xtal-clock",
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/linux/Documentation/devicetree/bindings/net/ieee802154/ |
H A D | at86rf230.txt | 15 - xtal-trim: u8 value for fine tuning the internal capacitance 16 arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF 26 xtal-trim = /bits/ 8 <0x06>;
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/linux/drivers/clk/mxs/ |
H A D | clk-imx23.c | 26 #define XTAL (CLKCTRL + 0x0050) macro 140 clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); in mx23_clocks_init() 141 clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28); in mx23_clocks_init() 142 clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); in mx23_clocks_init() 143 clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30); in mx23_clocks_init() 144 clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); in mx23_clocks_init()
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/linux/Documentation/devicetree/bindings/timer/ |
H A D | amlogic,meson6-timer.yaml | 29 - const: xtal 52 clocks = <&xtal>, <&clk81>; 53 clock-names = "xtal", "pclk";
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | amlogic,g12a-usb2-phy.yaml | 27 - const: xtal 76 clocks = <&xtal>; 77 clock-names = "xtal";
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/linux/drivers/clk/ |
H A D | clk-si5351.h | 154 * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input) 155 * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input) 156 * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input) 157 * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
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