Home
last modified time | relevance | path

Searched full:xtal (Results 1 – 25 of 318) sorted by relevance

12345678910>>...13

/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-xtal-clock.txt1 * Xtal Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
12 "marvell,armada-3700-xtal-clock"
17 output names ("xtal")
24 xtalclk: xtal-clk {
25 compatible = "marvell,armada-3700-xtal-clock";
26 clock-output-names = "xtal";
H A Dsilabs,si5351.yaml50 - const: xtal
62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
106 2 - use XTAL for this output
212 /* Connect XTAL input to 25MHz reference */
214 clock-names = "xtal";
216 /* Use XTAL input as source of PLL0 and PLL1 */
258 * - XTAL as clock source of output divider
H A Dmarvell,armada-3700-uart-clock.yaml23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
28 used for UART (most probably xtal) for smooth boot log on UART.
36 - const: xtal
57 clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
H A Damlogic,s4-pll-clkc.yaml25 - const: xtal
44 clocks = <&xtal>;
45 clock-names = "xtal";
H A Damlogic,meson8-ddr-clkc.yaml26 - const: xtal
45 clocks = <&xtal>;
46 clock-names = "xtal";
H A Dnxp,lpc3220-clk.yaml32 - const: xtal
49 clocks = <&xtal_32k>, <&xtal>;
50 clock-names = "xtal_32k", "xtal";
H A Dlpc1850-cgu.txt33 order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin.
81 xtal: xtal {
120 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
H A Damlogic,a1-peripherals-clkc.yaml43 - const: xtal
72 <&xtal>,
76 "hifi_pll", "xtal", "sys_pll";
/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-t7-a311d2-an400.dts27 xtal: xtal-clk { label
30 clock-output-names = "xtal";
36 clocks = <&xtal>, <&xtal>, <&xtal>;
37 clock-names = "xtal", "pclk", "baud";
H A Damlogic-t7-a311d2-khadas-vim4.dts41 xtal: xtal-clk { label
44 clock-output-names = "xtal";
52 clocks = <&xtal>, <&xtal>, <&xtal>;
53 clock-names = "xtal", "pclk", "baud";
H A Damlogic-a4-common.dtsi23 xtal: xtal-clk { label
26 clock-output-names = "xtal";
58 clocks = <&xtal>;
66 clocks = <&xtal>, <&xtal>, <&xtal>;
67 clock-names = "xtal", "pclk", "baud";
H A Dmeson-gxbb.dtsi286 clocks = <&xtal>, <&clkc CLKID_CLK81>;
287 clock-names = "xtal", "mpeg-clk";
322 assigned-clock-parents = <&xtal>, <0>;
330 clocks = <&xtal>;
331 clock-names = "xtal";
789 clocks = <&xtal>,
838 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
839 clock-names = "xtal", "pclk", "baud";
843 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
844 clock-names = "xtal", "pclk", "baud";
[all …]
H A Dmeson-gxl.dtsi310 clocks = <&xtal>, <&clkc CLKID_CLK81>;
311 clock-names = "xtal", "mpeg-clk";
334 assigned-clock-parents = <&xtal>, <0>;
342 clocks = <&xtal>;
343 clock-names = "xtal";
859 clocks = <&xtal>,
908 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
909 clock-names = "xtal", "pclk", "baud";
913 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
914 clock-names = "xtal", "pclk", "baud";
[all …]
H A Dmeson-s4.dtsi62 xtal: xtal-clk { label
65 clock-output-names = "xtal";
121 <&xtal>;
125 "mpll2", "mpll3", "hdmi_pll", "xtal";
132 clocks = <&xtal>;
133 clock-names = "xtal";
140 clocks = <&xtal>;
606 <&xtal>,
755 clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>;
756 clock-names = "xtal", "pclk", "baud";
[all …]
H A Dmeson-axg.dtsi1251 clocks = <&xtal>;
1252 clock-names = "xtal";
1575 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock-names = "xtal", "mpeg-clk";
1706 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1707 clock-names = "xtal", "pclk", "baud";
1715 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1716 clock-names = "xtal", "pclk", "baud";
1750 clocks = <&xtal>,
1805 clocks = <&xtal>;
[all …]
/linux/drivers/clk/pistachio/
H A Dclk-pistachio.c70 DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
105 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
106 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
107 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
109 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
110 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
112 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
113 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
114 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
117 PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
[all …]
/linux/drivers/media/pci/cx18/
H A Dcx18-av-audio.c66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
101 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
105 /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/ in set_audclk_freq()
109 /* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */ in set_audclk_freq()
136 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
140 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/ in set_audclk_freq()
144 /* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */ in set_audclk_freq()
173 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
[all …]
/linux/drivers/clk/renesas/
H A Drcar-usb2-clock-sel.c40 bool xtal; member
49 priv->extal, priv->xtal, val); in usb2_clock_sel_enable_extal_only()
51 if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) in usb2_clock_sel_enable_extal_only()
57 if (priv->extal && !priv->xtal) in usb2_clock_sel_disable_extal_only()
169 priv->xtal = !!clk_get_rate(clk); in rcar_usb2_clock_sel_probe()
173 if (!priv->extal && !priv->xtal) { in rcar_usb2_clock_sel_probe()
/linux/drivers/phy/ralink/
H A Dphy-mt7621-pci.c70 * @sys_clk: pointer to the system XTAL clock
127 /* Debug Xtal Type */ in mt7621_set_phy_for_ssc()
142 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
147 dev_dbg(dev, "Xtal is 40MHz\n"); in mt7621_set_phy_for_ssc()
174 dev_dbg(dev, "Xtal is 25MHz\n"); in mt7621_set_phy_for_ssc()
175 } else { /* 20MHz Xtal */ in mt7621_set_phy_for_ssc()
179 dev_dbg(dev, "Xtal is 20MHz\n"); in mt7621_set_phy_for_ssc()
199 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
/linux/drivers/clk/mvebu/
H A Darmada-37xx-xtal.c3 * Marvell Armada 37xx SoC xtal clocks
22 const char *xtal_name = "xtal"; in armada_3700_xtal_clock_probe()
74 { .compatible = "marvell,armada-3700-xtal-clock", },
82 .name = "marvell-armada-3700-xtal-clock",
/linux/Documentation/devicetree/bindings/net/ieee802154/
H A Dat86rf230.txt15 - xtal-trim: u8 value for fine tuning the internal capacitance
16 arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF
26 xtal-trim = /bits/ 8 <0x06>;
/linux/drivers/clk/mxs/
H A Dclk-imx23.c26 #define XTAL (CLKCTRL + 0x0050) macro
140 clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); in mx23_clocks_init()
141 clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28); in mx23_clocks_init()
142 clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); in mx23_clocks_init()
143 clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30); in mx23_clocks_init()
144 clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); in mx23_clocks_init()
/linux/Documentation/devicetree/bindings/timer/
H A Damlogic,meson6-timer.yaml29 - const: xtal
52 clocks = <&xtal>, <&clk81>;
53 clock-names = "xtal", "pclk";
/linux/Documentation/devicetree/bindings/phy/
H A Damlogic,g12a-usb2-phy.yaml27 - const: xtal
76 clocks = <&xtal>;
77 clock-names = "xtal";
/linux/drivers/clk/
H A Dclk-si5351.h154 * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
155 * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
156 * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
157 * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)

12345678910>>...13