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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
41 For list of all valid reset indices for Zynq UltraScale+ MPSoC see
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
14 The Zynq UltraScale+ MPSoC and Versal has several different resets.
25 For list of all valid reset indices for Zynq UltraScale+ MPSoC
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dxilinx-xadc.txt4 as the UltraScale/UltraScale+ System Monitor.
14 The Xilinx System Monitor is an ADC that is found in the UltraScale and
15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
29 UltraScale and UltraScale+ System Monitor.
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxlnx,zynqmp-clk.txt2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
22 Input clocks for zynqmp Ultrascale+ clock controller:
24 The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.yaml7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
H A Dxlnx,zynqmp-pcap-fpga.txt1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
/freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.txt15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
26 Zynq Ultrascale+ MPSoC
H A Dxlnx,zynqmp-firmware.yaml23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
/freebsd/sys/contrib/device-tree/Bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
40 Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcdns,macb.yaml24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
H A Dmacb.txt16 Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dxlnx-rtc.txt1 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
H A Dxlnx,zynqmp-rtc.yaml7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dcdns,uart.txt6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
H A Dcdns,uart.yaml19 - description: UART controller for Zynq Ultrascale+ MPSoC
/freebsd/sys/contrib/device-tree/Bindings/nvmem/
H A Dxlnx,zynqmp-nvmem.yaml7 title: Zynq UltraScale+ MPSoC Non Volatile Memory interface
H A Dxlnx,zynqmp-nvmem.txt2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-zynqmp-qspi.txt1 Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
H A Dspi-zynqmp-qspi.yaml7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
/freebsd/share/man/man4/
H A Dcgem.445 the Xilinx Zynq-7000, the Xilinx Zynq UltraScale+, and the SiFive
294 It is believed that the bug does not exist in the Zynq UltraScale+ and
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dxilinx.yaml13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
/freebsd/contrib/file/magic/Magdir/
H A Dxilinx78 >>0x2C lelong !0x01010000 \b, Zynq UltraScale+ MPSoC
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
H A Dxlnx,zynqmp-ipi-mailbox.txt5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
/freebsd/sys/contrib/device-tree/Bindings/soc/xilinx/
H A Dxilinx.yaml13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC

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