1 2#------------------------------------------------------------------------------ 3# $File: xilinx,v 1.12 2024/09/04 19:06:12 christos Exp $ 4# This is Aaron's attempt at a MAGIC file for Xilinx .bit files. 5# Xilinx-Magic@RevRagnarok.com 6# Got the info from FPGA-FAQ 0026 7# 8# Rewritten to use pstring/H instead of hardcoded lengths by O. Freyermuth, 9# fixes at least reading of bitfiles from Spartan 2, 3, 6. 10# http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm 11# 12# First there is the sync header and its length 130 beshort 0x0009 14>2 belong =0x0ff00ff0 15>>&0 belong =0x0ff00ff0 16>>>&0 byte =0x00 17>>>>&1 beshort =0x0001 18>>>>>&3 string a Xilinx BIT data 19# Next is a Pascal-style string with the NCD name. We want to capture that. 20>>>>>>&0 pstring/H x - from %s 21# And then 'b' 22>>>>>>>&1 string b 23# Then the model / part number: 24>>>>>>>>&0 pstring/H x - for %s 25# Then 'c' 26>>>>>>>>>&1 string c 27# Then the build-date 28>>>>>>>>>>&0 pstring/H x - built %s 29# Then 'd' 30>>>>>>>>>>>&1 string d 31# Then the build-time 32>>>>>>>>>>>>&0 pstring/H x \b(%s) 33# Then 'e' 34>>>>>>>>>>>>>&1 string e 35# And length of data 36>>>>>>>>>>>>>>&0 belong x - data length %#x 37 38# Raw bitstream files 390 long 0xffffffff 40>&0 belong 0xaa995566 Xilinx RAW bitstream (.BIN) 41 42# AXLF (xclbin) files used by AMD/Xilinx accelerators. 43# The file format is defined by XRT source tree: 44# https://github.com/Xilinx/XRT/blob/master/src/runtime_src/core/include/xclbin.h 45# Display file size, creation date, accelerator shell name, xclbin uuid and 46# number of sections. 47 480 string xclbin2 AMD/Xilinx accelerator AXLF (xclbin) file 49>0x130 lequad x \b, %lld bytes 50>0x138 leqdate x \b, created %s 51>0x160 string >0 \b, shell "%.64s" 52>0x1a0 ubelong x \b, uuid %08x 53>0x1a4 ubeshort x \b-%04x 54>0x1a6 ubeshort x \b-%04x 55>0x1a8 ubeshort x \b-%04x 56>0x1aa ubelong x \b-%08x 57>0x1ae ubeshort x \b%04x 58>0x1c0 lelong x \b, %d sections 59 60# Xilinx Boot Image files 61# File format spec is from Xilinx UG1283 62# https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide 630x20 lelong 0xAA995566 64>0x24 lelong 0x584c4e58 Xilinx Boot Image 65>>0x0 lelong 0xEAFFFFFE \b, 32-bit 66>>0x0 lelong 0x14000000 \b, 64-bit 67>>0x28 lelong 0x00000000 \b, unencrypted 68>>0x28 lelong 0xA5C3C5A5 \b, black key in efuse 69>>0x28 lelong 0xA5C3C5A7 \b, obfuscated key in efuse 70>>0x28 lelong 0x3A5C3C5A \b, red key in bbram 71>>0x28 lelong 0xA5C3C5A3 \b, efuse red key in efuse 72>>0x28 lelong 0xA35C7CA5 \b, obfuscated key in boot header 73>>0x28 lelong 0xA3A5C3C5 \b, user key in boot header 74>>0x28 lelong 0xA35C7C53 \b, black key in boot header 75>>0x2C lelong 0x01010000 \b, Zynq 7000 SoC 76!:mime application/x-xilinx-boot-zynq 77>>>0x34 ulelong >0 \b, FSBL size %#x bytes 78>>0x2C lelong !0x01010000 \b, Zynq UltraScale+ MPSoC 79!:mime application/x-xilinx-boot-zynqmp 80>>>0x34 ulelong >0 \b, PMU size %#x bytes 81>>>0x3C ulelong >0 \b, FSBL size %#x bytes 82