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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,ipq5332-uniphy-pcie-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
7 title: Qualcomm UNIPHY PCIe 28LP PHY
19 - qcom,ipq5018-uniphy-pcie-phy
20 - qcom,ipq5332-uniphy-pcie-phy
60 - qcom,ipq5018-uniphy-pcie-phy
76 - qcom,ipq5332-uniphy-pcie-phy
94 compatible = "qcom,ipq5332-uniphy-pcie-phy";
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq9574-nsscc.yaml77 <&uniphy 0>,
78 <&uniphy 1>,
79 <&uniphy 2>,
80 <&uniphy 3>,
81 <&uniphy 4>,
82 <&uniphy 5>,
H A Dqcom,ipq5018-gcc.yaml33 - description: UNIPHY RX clock source
34 - description: UNIPHY TX clk source
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn301/
H A Ddcn301_dio_link_encoder.c124 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn301_link_encoder_construct()
125 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn301_link_encoder_construct()
126 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn301_link_encoder_construct()
127 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn301_link_encoder_construct()
130 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn301_link_encoder_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_link_encoder.c156 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn201_link_encoder_construct()
157 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn201_link_encoder_construct()
158 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn201_link_encoder_construct()
159 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn201_link_encoder_construct()
162 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn201_link_encoder_construct()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_link_encoder.c135 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn30_link_encoder_construct()
136 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn30_link_encoder_construct()
137 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn30_link_encoder_construct()
138 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn30_link_encoder_construct()
141 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn30_link_encoder_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_link_encoder.c376 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn21_link_encoder_construct()
377 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn21_link_encoder_construct()
378 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn21_link_encoder_construct()
379 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn21_link_encoder_construct()
382 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn21_link_encoder_construct()
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-uniphy-pcie-28lp.c257 .compatible = "qcom,ipq5018-uniphy-pcie-phy",
260 .compatible = "qcom,ipq5332-uniphy-pcie-phy",
323 .name = "qcom-uniphy-pcie",
330 MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver");
H A DKconfig149 bool "PCIE UNIPHY 28LP PHY driver"
156 Enable this to support the PCIe UNIPHY 28LP phy transceiver that
H A DMakefile20 obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP) += phy-qcom-uniphy-pcie-28lp.o
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_link_encoder.c435 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn20_link_encoder_construct()
436 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn20_link_encoder_construct()
437 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn20_link_encoder_construct()
438 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn20_link_encoder_construct()
441 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn20_link_encoder_construct()
H A Ddcn20_link_encoder.h204 SRI(CHANNEL_XBAR_CNTL, UNIPHY, id)
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c850 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dce110_link_encoder_construct()
851 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dce110_link_encoder_construct()
852 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dce110_link_encoder_construct()
853 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dce110_link_encoder_construct()
856 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dce110_link_encoder_construct()
1752 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dce60_link_encoder_construct()
1753 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dce60_link_encoder_construct()
1754 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dce60_link_encoder_construct()
1755 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dce60_link_encoder_construct()
1758 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dce60_link_encoder_construct()
/linux/drivers/gpu/drm/radeon/
H A Datombios_crtc.c1842 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1844 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1851 * - PPLL0 is available to all UNIPHY (DP only)
1852 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1855 * - DCPLL is available to all UNIPHY (DP only)
1856 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1859 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1918 /* UNIPHY A uses PPLL2 */ in radeon_atom_pick_pll()
1921 /* UNIPHY B/C/D/E/F */ in radeon_atom_pick_pll()
1937 /* UNIPHY B/C/D/E/F */ in radeon_atom_pick_pll()
H A Datombios.h699 // =0: UNIPHY or PCIEPHY
953 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1025 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1026 // =1 Dig Transmitter 2 ( Uniphy CD )
1027 // =2 Dig Transmitter 3 ( Uniphy EF )
1031 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1032 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1039 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1040 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1044 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h835 // =0: UNIPHY or PCIEPHY
1159 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1231 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1232 // =1 Dig Transmitter 2 ( Uniphy CD )
1233 // =2 Dig Transmitter 3 ( Uniphy EF )
1237 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1238 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1245 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1246 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1250 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_link_encoder.h114 /* UNIPHY */
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c2140 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2142 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
H A Ddce_v10_0.c2232 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2234 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
H A Datombios_encoders.c543 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)