1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dcn20_link_encoder.h"
31 #include "stream_encoder.h"
32 #include "dc_bios_types.h"
33
34 #include "gpio_service_interface.h"
35
36 #define CTX \
37 enc10->base.ctx
38 #define DC_LOGGER \
39 enc10->base.ctx->logger
40
41 #define REG(reg)\
42 (enc10->link_regs->reg)
43
44 #undef FN
45 #define FN(reg_name, field_name) \
46 enc10->link_shift->field_name, enc10->link_mask->field_name
47
48 #define IND_REG(index) \
49 (enc10->link_regs->index)
50
51 #ifndef MAX
52 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
53 #endif
54 #ifndef MIN
55 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
56 #endif
57
58 static struct mpll_cfg dcn2_mpll_cfg[] = {
59 // RBR
60 {
61 .hdmimode_enable = 1,
62 .ref_range = 3,
63 .ref_clk_mpllb_div = 2,
64 .mpllb_ssc_en = 1,
65 .mpllb_div5_clk_en = 1,
66 .mpllb_multiplier = 226,
67 .mpllb_fracn_en = 1,
68 .mpllb_fracn_quot = 39321,
69 .mpllb_fracn_rem = 3,
70 .mpllb_fracn_den = 5,
71 .mpllb_ssc_up_spread = 0,
72 .mpllb_ssc_peak = 38221,
73 .mpllb_ssc_stepsize = 49314,
74 .mpllb_div_clk_en = 0,
75 .mpllb_div_multiplier = 0,
76 .mpllb_hdmi_div = 0,
77 .mpllb_tx_clk_div = 2,
78 .tx_vboost_lvl = 4,
79 .mpllb_pmix_en = 1,
80 .mpllb_word_div2_en = 0,
81 .mpllb_ana_v2i = 2,
82 .mpllb_ana_freq_vco = 2,
83 .mpllb_ana_cp_int = 7,
84 .mpllb_ana_cp_prop = 18,
85 .hdmi_pixel_clk_div = 0,
86 },
87 // HBR
88 {
89 .hdmimode_enable = 1,
90 .ref_range = 3,
91 .ref_clk_mpllb_div = 2,
92 .mpllb_ssc_en = 1,
93 .mpllb_div5_clk_en = 1,
94 .mpllb_multiplier = 184,
95 .mpllb_fracn_en = 0,
96 .mpllb_fracn_quot = 0,
97 .mpllb_fracn_rem = 0,
98 .mpllb_fracn_den = 1,
99 .mpllb_ssc_up_spread = 0,
100 .mpllb_ssc_peak = 31850,
101 .mpllb_ssc_stepsize = 41095,
102 .mpllb_div_clk_en = 0,
103 .mpllb_div_multiplier = 0,
104 .mpllb_hdmi_div = 0,
105 .mpllb_tx_clk_div = 1,
106 .tx_vboost_lvl = 4,
107 .mpllb_pmix_en = 1,
108 .mpllb_word_div2_en = 0,
109 .mpllb_ana_v2i = 2,
110 .mpllb_ana_freq_vco = 3,
111 .mpllb_ana_cp_int = 7,
112 .mpllb_ana_cp_prop = 18,
113 .hdmi_pixel_clk_div = 0,
114 },
115 //HBR2
116 {
117 .hdmimode_enable = 1,
118 .ref_range = 3,
119 .ref_clk_mpllb_div = 2,
120 .mpllb_ssc_en = 1,
121 .mpllb_div5_clk_en = 1,
122 .mpllb_multiplier = 184,
123 .mpllb_fracn_en = 0,
124 .mpllb_fracn_quot = 0,
125 .mpllb_fracn_rem = 0,
126 .mpllb_fracn_den = 1,
127 .mpllb_ssc_up_spread = 0,
128 .mpllb_ssc_peak = 31850,
129 .mpllb_ssc_stepsize = 41095,
130 .mpllb_div_clk_en = 0,
131 .mpllb_div_multiplier = 0,
132 .mpllb_hdmi_div = 0,
133 .mpllb_tx_clk_div = 0,
134 .tx_vboost_lvl = 4,
135 .mpllb_pmix_en = 1,
136 .mpllb_word_div2_en = 0,
137 .mpllb_ana_v2i = 2,
138 .mpllb_ana_freq_vco = 3,
139 .mpllb_ana_cp_int = 7,
140 .mpllb_ana_cp_prop = 18,
141 .hdmi_pixel_clk_div = 0,
142 },
143 //HBR3
144 {
145 .hdmimode_enable = 1,
146 .ref_range = 3,
147 .ref_clk_mpllb_div = 2,
148 .mpllb_ssc_en = 1,
149 .mpllb_div5_clk_en = 1,
150 .mpllb_multiplier = 292,
151 .mpllb_fracn_en = 0,
152 .mpllb_fracn_quot = 0,
153 .mpllb_fracn_rem = 0,
154 .mpllb_fracn_den = 1,
155 .mpllb_ssc_up_spread = 0,
156 .mpllb_ssc_peak = 47776,
157 .mpllb_ssc_stepsize = 61642,
158 .mpllb_div_clk_en = 0,
159 .mpllb_div_multiplier = 0,
160 .mpllb_hdmi_div = 0,
161 .mpllb_tx_clk_div = 0,
162 .tx_vboost_lvl = 4,
163 .mpllb_pmix_en = 1,
164 .mpllb_word_div2_en = 0,
165 .mpllb_ana_v2i = 2,
166 .mpllb_ana_freq_vco = 0,
167 .mpllb_ana_cp_int = 7,
168 .mpllb_ana_cp_prop = 18,
169 .hdmi_pixel_clk_div = 0,
170 },
171 };
172
enc2_fec_set_enable(struct link_encoder * enc,bool enable)173 void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
174 {
175 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
176 DC_LOG_DSC("%s FEC at link encoder inst %d",
177 enable ? "Enabling" : "Disabling", enc->id.enum_id);
178 REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
179 }
180
enc2_fec_set_ready(struct link_encoder * enc,bool ready)181 void enc2_fec_set_ready(struct link_encoder *enc, bool ready)
182 {
183 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
184
185 REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready);
186 }
187
enc2_fec_is_active(struct link_encoder * enc)188 bool enc2_fec_is_active(struct link_encoder *enc)
189 {
190 uint32_t active = 0;
191 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
192
193 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active);
194
195 return (active != 0);
196 }
197
198 /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state
199 * into a dcn_dsc_state struct.
200 */
link_enc2_read_state(struct link_encoder * enc,struct link_enc_state * s)201 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
202 {
203 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
204
205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
208 REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
209 }
210
update_cfg_data(struct dcn10_link_encoder * enc10,const struct dc_link_settings * link_settings,struct dpcssys_phy_seq_cfg * cfg)211 static bool update_cfg_data(
212 struct dcn10_link_encoder *enc10,
213 const struct dc_link_settings *link_settings,
214 struct dpcssys_phy_seq_cfg *cfg)
215 {
216 int i;
217
218 cfg->load_sram_fw = false;
219
220 for (i = 0; i < link_settings->lane_count; i++)
221 cfg->lane_en[i] = true;
222
223 switch (link_settings->link_rate) {
224 case LINK_RATE_LOW:
225 cfg->mpll_cfg = dcn2_mpll_cfg[0];
226 break;
227 case LINK_RATE_HIGH:
228 cfg->mpll_cfg = dcn2_mpll_cfg[1];
229 break;
230 case LINK_RATE_HIGH2:
231 cfg->mpll_cfg = dcn2_mpll_cfg[2];
232 break;
233 case LINK_RATE_HIGH3:
234 cfg->mpll_cfg = dcn2_mpll_cfg[3];
235 break;
236 default:
237 DC_LOG_ERROR("%s: No supported link rate found %X!\n",
238 __func__, link_settings->link_rate);
239 return false;
240 }
241
242 return true;
243 }
244
dcn20_link_encoder_enable_dp_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)245 void dcn20_link_encoder_enable_dp_output(
246 struct link_encoder *enc,
247 const struct dc_link_settings *link_settings,
248 enum clock_source_id clock_source)
249 {
250 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
251 struct dcn20_link_encoder *enc20 = (struct dcn20_link_encoder *) enc10;
252 struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg;
253
254 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
255 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
256 return;
257 }
258
259 if (!update_cfg_data(enc10, link_settings, cfg))
260 return;
261
262 enc1_configure_encoder(enc10, link_settings);
263
264 dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
265
266 }
267
dcn20_link_encoder_get_max_link_cap(struct link_encoder * enc,struct dc_link_settings * link_settings)268 void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,
269 struct dc_link_settings *link_settings)
270 {
271 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
272 uint32_t is_in_usb_c_dp4_mode = 0;
273
274 dcn10_link_encoder_get_max_link_cap(enc, link_settings);
275
276 /* in usb c dp2 mode, max lane count is 2 */
277 if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
278 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
279 if (!is_in_usb_c_dp4_mode)
280 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
281 }
282
283 }
284
dcn20_link_encoder_is_in_alt_mode(struct link_encoder * enc)285 bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc)
286 {
287 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
288 uint32_t dp_alt_mode_disable = 0;
289 bool is_usb_c_alt_mode = false;
290
291 if (enc->features.flags.bits.DP_IS_USB_C) {
292 /* if value == 1 alt mode is disabled, otherwise it is enabled */
293 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
294 is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
295 }
296
297 return is_usb_c_alt_mode;
298 }
299
300 #define AUX_REG(reg)\
301 (enc10->aux_regs->reg)
302
303 #define AUX_REG_READ(reg_name) \
304 dm_read_reg(CTX, AUX_REG(reg_name))
305
306 #define AUX_REG_WRITE(reg_name, val) \
307 dm_write_reg(CTX, AUX_REG(reg_name), val)
enc2_hw_init(struct link_encoder * enc)308 void enc2_hw_init(struct link_encoder *enc)
309 {
310 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
311 /*
312 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
313 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
314 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
315 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
316 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
317 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
318 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
319 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
320 */
321
322 /*
323 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
324 AUX_RX_START_WINDOW = 1 [6:4]
325 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
326 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
327 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
328 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
329 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
330 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
331 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
332 AUX_RX_DETECTION_THRESHOLD [30:28] = 1
333 */
334 if (enc->ctx->dc_bios->golden_table.dc_golden_table_ver > 0) {
335 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control0_val);
336
337 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, enc->ctx->dc_bios->golden_table.aux_dphy_tx_control_val);
338
339 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL1, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control1_val);
340 } else {
341 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
342
343 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
344 }
345
346 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
347 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
348 // 27MHz -> 0xd
349 // 100MHz -> 0x32
350 // 48MHz -> 0x18
351
352 // Set TMDS_CTL0 to 1. This is a legacy setting.
353 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
354
355 dcn10_aux_initialize(enc10);
356 }
357
358 static const struct link_encoder_funcs dcn20_link_enc_funcs = {
359 .read_state = link_enc2_read_state,
360 .validate_output_with_stream =
361 dcn10_link_encoder_validate_output_with_stream,
362 .hw_init = enc2_hw_init,
363 .setup = dcn10_link_encoder_setup,
364 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa,
365 .enable_dp_output = dcn20_link_encoder_enable_dp_output,
366 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
367 .disable_output = dcn10_link_encoder_disable_output,
368 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
369 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
370 .update_mst_stream_allocation_table =
371 dcn10_link_encoder_update_mst_stream_allocation_table,
372 .psr_program_dp_dphy_fast_training =
373 dcn10_psr_program_dp_dphy_fast_training,
374 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
375 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
376 .enable_hpd = dcn10_link_encoder_enable_hpd,
377 .disable_hpd = dcn10_link_encoder_disable_hpd,
378 .is_dig_enabled = dcn10_is_dig_enabled,
379 .destroy = dcn10_link_encoder_destroy,
380 .fec_set_enable = enc2_fec_set_enable,
381 .fec_set_ready = enc2_fec_set_ready,
382 .fec_is_active = enc2_fec_is_active,
383 .get_dig_mode = dcn10_get_dig_mode,
384 .get_dig_frontend = dcn10_get_dig_frontend,
385 .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
386 .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
387 };
388
dcn20_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)389 void dcn20_link_encoder_construct(
390 struct dcn20_link_encoder *enc20,
391 const struct encoder_init_data *init_data,
392 const struct encoder_feature_support *enc_features,
393 const struct dcn10_link_enc_registers *link_regs,
394 const struct dcn10_link_enc_aux_registers *aux_regs,
395 const struct dcn10_link_enc_hpd_registers *hpd_regs,
396 const struct dcn10_link_enc_shift *link_shift,
397 const struct dcn10_link_enc_mask *link_mask)
398 {
399 struct bp_encoder_cap_info bp_cap_info = {0};
400 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
401 enum bp_result result = BP_RESULT_OK;
402 struct dcn10_link_encoder *enc10 = &enc20->enc10;
403
404 enc10->base.funcs = &dcn20_link_enc_funcs;
405 enc10->base.ctx = init_data->ctx;
406 enc10->base.id = init_data->encoder;
407
408 enc10->base.hpd_source = init_data->hpd_source;
409 enc10->base.connector = init_data->connector;
410
411 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
412
413 enc10->base.features = *enc_features;
414
415 enc10->base.transmitter = init_data->transmitter;
416
417 /* set the flag to indicate whether driver poll the I2C data pin
418 * while doing the DP sink detect
419 */
420
421 /* if (dal_adapter_service_is_feature_supported(as,
422 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
423 enc10->base.features.flags.bits.
424 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
425
426 enc10->base.output_signals =
427 SIGNAL_TYPE_DVI_SINGLE_LINK |
428 SIGNAL_TYPE_DVI_DUAL_LINK |
429 SIGNAL_TYPE_LVDS |
430 SIGNAL_TYPE_DISPLAY_PORT |
431 SIGNAL_TYPE_DISPLAY_PORT_MST |
432 SIGNAL_TYPE_EDP |
433 SIGNAL_TYPE_HDMI_TYPE_A;
434
435 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
436 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
437 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
438 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
439 * Prefer DIG assignment is decided by board design.
440 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
441 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
442 * By this, adding DIGG should not hurt DCE 8.0.
443 * This will let DCE 8.1 share DCE 8.0 as much as possible
444 */
445
446 enc10->link_regs = link_regs;
447 enc10->aux_regs = aux_regs;
448 enc10->hpd_regs = hpd_regs;
449 enc10->link_shift = link_shift;
450 enc10->link_mask = link_mask;
451
452 switch (enc10->base.transmitter) {
453 case TRANSMITTER_UNIPHY_A:
454 enc10->base.preferred_engine = ENGINE_ID_DIGA;
455 break;
456 case TRANSMITTER_UNIPHY_B:
457 enc10->base.preferred_engine = ENGINE_ID_DIGB;
458 break;
459 case TRANSMITTER_UNIPHY_C:
460 enc10->base.preferred_engine = ENGINE_ID_DIGC;
461 break;
462 case TRANSMITTER_UNIPHY_D:
463 enc10->base.preferred_engine = ENGINE_ID_DIGD;
464 break;
465 case TRANSMITTER_UNIPHY_E:
466 enc10->base.preferred_engine = ENGINE_ID_DIGE;
467 break;
468 case TRANSMITTER_UNIPHY_F:
469 enc10->base.preferred_engine = ENGINE_ID_DIGF;
470 break;
471 case TRANSMITTER_UNIPHY_G:
472 enc10->base.preferred_engine = ENGINE_ID_DIGG;
473 break;
474 default:
475 ASSERT_CRITICAL(false);
476 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
477 }
478
479 /* default to one to mirror Windows behavior */
480 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
481
482 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
483 enc10->base.id, &bp_cap_info);
484
485 /* Override features with DCE-specific values */
486 if (result == BP_RESULT_OK) {
487 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
488 bp_cap_info.DP_HBR2_EN;
489 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
490 bp_cap_info.DP_HBR3_EN;
491 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
492 enc10->base.features.flags.bits.DP_IS_USB_C =
493 bp_cap_info.DP_IS_USB_C;
494 } else {
495 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
496 __func__,
497 result);
498 }
499 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
500 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
501 }
502 }
503