| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | mediatek,uart.yaml | 4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6580-uart
29 - mediatek,mt6582-uart
30 - mediatek,mt6589-uart
31 - mediatek,mt6755-uart
[all …]
|
| H A D | mtk-uart.txt | 1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
13 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
[all …]
|
| H A D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
18 for standard variant of UART and UART2-clk for extended variant
19 of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock
23 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
24 respectively the UART sum interrupt, the UART TX interrupt and
[all …]
|
| H A D | samsung_uart.yaml | 7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
22 - apple,s5l-uart
23 - axis,artpec8-uart
24 - google,gs101-uart
25 - samsung,s3c6400-uart
26 - samsung,s5pv210-uart
27 - samsung,exynos4210-uart
28 - samsung,exynos5433-uart
29 - samsung,exynos850-uart
[all …]
|
| H A D | amlogic,meson-uart.yaml | 5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#
8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
28 - description: Always-on power domain UART controller
31 - amlogic,meson6-uart
32 - amlogic,meson8-uart
33 - amlogic,meson8b-uart
34 - amlogic,meson-gx-uart
35 - amlogic,meson-s4-uart
36 - amlogic,meson-a1-uart
[all …]
|
| H A D | snps-dw-apb-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 const: starfive,jh7110-uart
35 - renesas,r9a06g032-uart
36 - renesas,r9a06g033-uart
37 - const: renesas,rzn1-uart
40 - rockchip,px30-uart
41 - rockchip,rk1808-uart
42 - rockchip,rk3036-uart
43 - rockchip,rk3066-uart
[all …]
|
| H A D | fsl-imx-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
19 - fsl,imx25-uart
20 - fsl,imx27-uart
21 - fsl,imx31-uart
22 - fsl,imx35-uart
23 - fsl,imx50-uart
24 - fsl,imx51-uart
[all...] |
| H A D | 8250.yaml | 7 title: UART (Universal Asynchronous Receiver/Transmitter)
30 const: mrvl,mmp-uart
62 - const: intel,xscale-uart
63 - const: mrvl,pxa-uart
64 - const: nuvoton,wpcm450-uart
65 - const: nuvoton,npcm750-uart
66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart
82 - nxp,lpc1850-uart
84 - ti,da830-uart
[all …]
|
| H A D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
7 - interrupts : Should contain uart interrupt
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
20 compatible = "sirf,prima2-uart";
30 compatible = "sirf,prima2-usp-uart";
[all …]
|
| H A D | omap_serial.txt | 1 OMAP UART controller
4 - compatible : should be "ti,am64-uart", "ti,am654-uart" for AM64 controllers
5 - compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
6 - compatible : should be "ti,am654-uart" for AM654 controllers
7 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
8 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
9 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
10 - compatible : should be "ti,am4372-uart" for AM437x controllers
11 - compatible : should be "ti,am3352-uart" for AM335x controllers
12 - compatible : should be "ti,dra742-uart" for DRA7x controllers
[all …]
|
| H A D | sprd-uart.yaml | 5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
8 title: Spreadtrum serial UART
20 - sprd,sc9860-uart
21 - sprd,sc9863a-uart
22 - sprd,ums512-uart
23 - sprd,ums9620-uart
24 - const: sprd,sc9836-uart
25 - const: sprd,sc9836-uart
39 "enable" for UART module enable clock, "uart" fo
[all...] |
| H A D | brcm,bcm7271-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
32 description: The UART register block and optionally the DMA register blocks.
35 - const: uart
37 - const: uart
54 description: The UART interrupt and optionally the DMA interrupt.
57 - const: uart
74 compatible = "brcm,bcm7271-uart";
[all …]
|
| H A D | ingenic,uart.yaml | 4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
7 title: Ingenic SoCs UART controller
22 - ingenic,jz4740-uart
23 - ingenic,jz4750-uart
24 - ingenic,jz4760-uart
25 - ingenic,jz4780-uart
26 - ingenic,x1000-uart
29 - ingenic,jz4770-uart
30 - ingenic,jz4775-uart
31 - const: ingenic,jz4760-uart
[all …]
|
| H A D | 8250_omap.yaml | 20 - ti,am3352-uart
21 - ti,am4372-uart
22 - ti,am654-uart
23 - ti,dra742-uart
24 - ti,omap2-uart
25 - ti,omap3-uart
26 - ti,omap4-uart
29 - ti,am64-uart
30 - ti,j721e-uart
31 - const: ti,am654-uart
[all …]
|
| H A D | fsl-imx-uart.txt | 1 * Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible : Should be "fsl,<soc>-uart"
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
18 properties. In case you use "uart-has-rtscts" the signal that controls
25 Note: Each uart controller should have an alias correctly numbered
35 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
38 uart-has-rtscts;
|
| H A D | serial.yaml | 18 Each enabled UART may have an optional "serialN" alias in the "aliases" node,
32 the UART's CTS line.
38 the UART's DCD line.
44 the UART's DSR line.
50 the UART's DTR line.
56 the UART's RNG line.
62 the UART's RTS line.
64 uart-has-rtscts:
67 The presence of this property indicates that the UART has dedicated lines
70 UART hardware and the board wiring.
[all …]
|
| H A D | renesas,em-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
7 title: Renesas EMMA Mobile UART Interface
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
21 - const: renesas,em-uart # generic EMMA Mobile compatible UART
32 - description: UART functional clock
55 const: renesas,r9a09g011-uart
69 compatible = "renesas,em-uart";
[all...] |
| H A D | sifive-serial.yaml | 7 title: SiFive asynchronous serial interface (UART)
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
27 Should be something similar to "sifive,<chip>-uart"
28 for the UART as integrated on a particular chip,
29 and "sifive,uart<version>" for the general UART IP
32 UART HDL that corresponds to the IP block version
35 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
58 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
|
| H A D | cdns,uart.txt | 1 Binding for Cadence UART Controller
5 Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
7 - reg: Should contain UART controller registers location and length.
8 - interrupts: Should contain UART controller interrupts.
9 - clocks: Must contain phandles to the UART clocks
21 uart@e0000000 {
22 compatible = "cdns,uart-r1p8";
|
| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | mediatek,uart-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
24 - mediatek,mt2712-uart-dma
25 - mediatek,mt6795-uart-dma
26 - mediatek,mt8365-uart-dma
27 - mediatek,mt8516-uart-dma
28 - const: mediatek,mt6577-uart-dma
30 - mediatek,mt6577-uart-dma
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | uart.4 | 32 .Nm uart
35 .Cd "device uart"
38 .Cd "device uart"
41 .Cd "device uart"
45 .Cd hint.uart.0.disabled="1"
46 .Cd hint.uart.0.baud="38400"
47 .Cd hint.uart.0.port="0x3f8"
48 .Cd hint.uart.0.flags="0x10"
124 Such an UART cannot be used for general purpose communications.
126 corresponding UART will in turn be a system device so that the kernel can
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-mt7622.txt | 196 "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
306 "uart0_0_tx_rx" "uart" 6, 7
307 "uart1_0_tx_rx" "uart" 55, 56
308 "uart1_0_rts_cts" "uart" 57, 58
309 "uart1_1_tx_rx" "uart" 73, 74
310 "uart1_1_rts_cts" "uart" 75, 76
311 "uart2_0_tx_rx" "uart" 3, 4
312 "uart2_0_rts_cts" "uart" 1, 2
313 "uart2_1_tx_rx" "uart" 51, 52
314 "uart2_1_rts_cts" "uart" 53, 54
[all …]
|
| /freebsd/sys/dev/uart/ |
| H A D | uart_dev_msm.h | 33 /* UART Parity Mode */
41 /* UART Stop Bit Length */
49 /* UART Bits per Char */
64 /* UART Operational Mode Registers (HSUART) */
79 /* UART Clock Selection Register, write only */
82 /* UART DM TX FIFO Registers - 4, write only */
85 /* UART Command Register, write only */
111 /* UART Interrupt Mask Register */
133 /* UART Interrupt Programming Register */
140 /* UART Transmit/Receive FIFO Watermark Register */
[all …]
|
| /freebsd/bin/kenv/ |
| H A D | kenv.1 | 122 Show kernel probe hints variable names and filter for the uart
125 $ kenv -h -N | grep uart
126 hint.uart.0.at
127 hint.uart.0.flags
128 hint.uart.0.irq
129 hint.uart.0.port
130 hint.uart.1.at
131 hint.uart.1.irq
132 hint.uart.1.port
137 $ kenv hint.uart.1.at
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/aspeed/ |
| H A D | uart-routing.yaml | 6 $id: http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#
9 title: Aspeed UART Routing Controller
16 The Aspeed UART routing control allow to dynamically route the inputs for
19 This allows, for example, to connect the output of UART to another UART.
31 - aspeed,ast2400-uart-routing
32 - aspeed,ast2500-uart-routing
33 - aspeed,ast2600-uart-routing
52 uart_routing: uart-routing@98 {
53 compatible = "aspeed,ast2600-uart
[all...] |