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/linux/Documentation/driver-api/firmware/
H A Dother_interfaces.rst22 Intel Stratix10 SoC Service Layer
24 Some features of the Intel Stratix10 SoC require a level of privilege
30 The Intel Stratix10 SoC service layer provides an in kernel API for
35 .. kernel-doc:: include/linux/firmware/intel/stratix10-svc-client.h
38 .. kernel-doc:: include/linux/firmware/intel/stratix10-svc-client.h
41 .. kernel-doc:: include/linux/firmware/intel/stratix10-svc-client.h
44 .. kernel-doc:: include/linux/firmware/intel/stratix10-svc-client.h
47 .. kernel-doc:: include/linux/firmware/intel/stratix10-svc-client.h
50 .. kernel-doc:: drivers/firmware/stratix10-svc.c
/linux/Documentation/devicetree/bindings/fpga/
H A Dintel,stratix10-soc-fpga-mgr.yaml4 $id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml#
7 title: Intel Stratix10 SoC FPGA Manager
15 The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard
16 processor system (HPS) and a Secure Device Manager (SDM). The Stratix10
18 on the die.The driver communicates with SDM/ATF via the stratix10-svc
24 - intel,stratix10-soc-fpga-mgr
35 compatible = "intel,stratix10-soc-fpga-mgr";
/linux/Documentation/devicetree/bindings/firmware/
H A Dintel,stratix10-svc.yaml4 $id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml#
7 title: Intel Service Layer Driver for Stratix10 SoC
14 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
26 Intel Stratix10 service layer driver, running at privileged exception level
35 - intel,stratix10-svc
62 $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
99 compatible = "intel,stratix10-svc";
104 compatible = "intel,stratix10-soc-fpga-mgr";
/linux/Documentation/devicetree/bindings/clock/
H A Dintel,stratix10.yaml4 $id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
7 title: Intel SoCFPGA Stratix10 platform clock controller
14 const: intel,stratix10-clkmgr
32 compatible = "intel,stratix10-clkmgr";
/linux/Documentation/devicetree/bindings/reset/
H A Daltr,rst-mgr.yaml17 - description: Stratix10 ARM64 SoC
19 - const: altr,stratix10-rst-mgr
41 const: altr,stratix10-rst-mgr
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_swvp.dts10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
/linux/Documentation/devicetree/bindings/net/
H A Daltr,socfpga-stmmac.yaml14 Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
152 bits, while on the Arria10/Stratix10/Agilex platforms, the
/linux/drivers/clk/socfpga/
H A Dclk-s10.c10 #include <dt-bindings/clock/stratix10-clock.h>
12 #include "stratix10-clk.h"
433 { .compatible = "intel,stratix10-clkmgr",
441 .name = "stratix10-clkmgr",
H A Dclk-periph-s10.c9 #include "stratix10-clk.h"
H A Dclk-gate-s10.c8 #include "stratix10-clk.h"
H A Dclk-pll-s10.c9 #include "stratix10-clk.h"
H A Dclk-agilex5.c11 #include "stratix10-clk.h"
H A Dclk-agilex.c12 #include "stratix10-clk.h"
/linux/include/linux/mfd/
H A Daltera-sysmgr.h13 #include <linux/firmware/intel/stratix10-smc.h>
/linux/drivers/edac/
H A Daltera_edac.h292 /************* Stratix10 Defines **************/
318 /* Stratix10 ECC Manager Defines */
H A Daltera_edac.c12 #include <linux/firmware/intel/stratix10-smc.h>
1769 * The Stratix10 EDAC Error Injection Functions differ from Arria10
/linux/drivers/reset/
H A Dreset-simple.c137 { .compatible = "altr,stratix10-rst-mgr",
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi398 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
/linux/drivers/usb/dwc2/
H A Dcore.h1029 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
/linux/
H A DMAINTAINERS13489 INTEL STRATIX10 FIRMWARE DRIVERS
13494 F: Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu
13495 F: Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
13496 F: drivers/firmware/stratix10-rsu.c
13497 F: drivers/firmware/stratix10-svc.c
13498 F: include/linux/firmware/intel/stratix10-smc.h
13499 F: include/linux/firmware/intel/stratix10-svc-client.h