| /linux/drivers/pcmcia/ |
| H A D | sa1111_generic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <asm/mach-types.h>
70 struct sa1111_pcmcia_socket *s = to_skt(skt); in sa1111_pcmcia_socket_state() local
71 u32 status = readl_relaxed(s->dev->mapbase + PCSR); in sa1111_pcmcia_socket_state()
73 switch (skt->nr) { in sa1111_pcmcia_socket_state()
75 state->detect = status & PCSR_S0_DETECT ? 0 : 1; in sa1111_pcmcia_socket_state()
76 state->ready = status & PCSR_S0_READY ? 1 : 0; in sa1111_pcmcia_socket_state()
77 state->bvd1 = status & PCSR_S0_BVD1 ? 1 : 0; in sa1111_pcmcia_socket_state()
78 state->bvd2 = status & PCSR_S0_BVD2 ? 1 : 0; in sa1111_pcmcia_socket_state()
79 state->wrprot = status & PCSR_S0_WP ? 1 : 0; in sa1111_pcmcia_socket_state()
[all …]
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-devices-soc | 5 The /sys/devices/ directory contains a sub-directory for each
6 System-on-Chip (SoC) device on a running platform. Information
7 regarding each SoC can be obtained by reading sysfs files. This
10 The directory created for each SoC will also house information
12 It has been agreed that if an SoC device exists, its supported
13 devices would be better suited to appear as children of that SoC.
19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
30 this will contain the JEDEC JEP106 manufacturer’s identification
34 This manufacturer’s identification code is defined by one
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| /linux/arch/arm/mach-at91/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
18 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
22 Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
38 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
49 Select this if you are using one of Microchip's SAMA5D3 family SoC.
63 Select this if you are using one of Microchip's SAMA5D4 family SoC.
74 Select this if you are using one of Microchip's SAMA7D65 family SoC.
85 Select this if you are using one of Microchip's SAMA7G5 family SoC.
88 bool "ARMv7 based Microchip LAN966 SoC family"
94 This enables support for ARMv7 based Microchip LAN966 SoC family.
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| /linux/drivers/pinctrl/freescale/ |
| H A D | pinctrl-mxs.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include "pinctrl-mxs.h"
28 struct mxs_pinctrl_soc_data *soc; member
35 return d->soc->ngroups; in mxs_get_groups_count()
43 return d->soc->groups[group].name; in mxs_get_group_name()
51 *pins = d->soc->groups[group].pins; in mxs_get_group_pins()
52 *num_pins = d->soc->groups[group].npins; in mxs_get_group_pins()
57 static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, in mxs_pin_dbg_show() argument
60 seq_printf(s, " %s", dev_name(pctldev->dev)); in mxs_pin_dbg_show()
72 int length = strlen(np->name) + SUFFIX_LEN; in mxs_dt_node_to_map()
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| /linux/drivers/phy/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Exynos SoC series Display Port PHY driver"
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
29 Enable PCIe PHY support for Exynos SoC series.
33 tristate "Exynos SoC series UFS PHY driver"
38 Enable this to support the Samsung Exynos SoC UFS PHY driver for
43 tristate "S5P/Exynos SoC series USB 2.0 PHY driver"
52 2.0 PHY. Support for particular PHYs will be enabled based on the SoC
77 particular SoC is compiled in the driver. In case of S5PV210 two phys
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| /linux/drivers/phy/tegra/ |
| H A D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
20 #include <soc/tegra/fuse.h>
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
[all …]
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| /linux/drivers/memory/tegra/ |
| H A D | mc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
20 #include <soc/tegra/fuse.h>
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
[all …]
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| H A D | tegra20.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <dt-bindings/memory/tegra20-mc.h>
285 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_assert()
287 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
288 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
290 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_assert()
301 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_deassert()
303 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_deassert()
304 mc_writel(mc, value | BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_deassert()
306 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_deassert()
[all …]
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| /linux/drivers/bus/ |
| H A D | mvebu-mbus.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 * - One to configure the access of the CPU to the devices. Depending
17 * - One to configure the access to the CPU to the SDRAM. There are
23 * - Reads out the SDRAM address decoding windows at initialization
30 * devices have to configure those device -> SDRAM windows to ensure
33 * - Provides an API for platform code or device drivers to
34 * dynamically add or remove address decoding windows for the CPU ->
39 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
40 * see the list of CPU -> SDRAM windows and their configuration
41 * (file 'sdram') and the list of CPU -> devices windows and their
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| /linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
24 #include "pinctrl-mvebu.h"
64 *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; in mvebu_mmio_mpp_ctrl_get()
76 reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); in mvebu_mmio_mpp_ctrl_set()
77 writel(reg | (config << shift), data->base + off); in mvebu_mmio_mpp_ctrl_set()
86 for (n = 0; n < pctl->num_groups; n++) { in mvebu_pinctrl_find_group_by_pid()
87 if (pid >= pctl->groups[n].pins[0] && in mvebu_pinctrl_find_group_by_pid()
88 pid < pctl->groups[n].pins[0] + in mvebu_pinctrl_find_group_by_pid()
89 pctl->groups[n].npins) in mvebu_pinctrl_find_group_by_pid()
[all …]
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| /linux/drivers/iommu/ |
| H A D | tegra-smmu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
17 #include <linux/dma-mapping.h>
19 #include <soc/tegra/ahb.h>
20 #include <soc/tegra/mc.h>
22 #include "iommu-pages.h"
27 const struct tegra_smmu_group_soc *soc; member
37 const struct tegra_smmu_soc *soc; member
78 writel(value, smmu->regs + offset); in smmu_writel()
83 return readl(smmu->regs + offset); in smmu_readl()
[all …]
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| /linux/drivers/reset/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
37 AR71xx SoC reset controller.
94 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
97 If compiled as module, it will be called reset-gpio.
141 bool "Reset controller driver for Canaan Kendryte K210 SoC"
146 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
151 tristate "Reset controller driver for Canaan Kendryte K230 SoC"
155 Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
177 This driver supports switch core reset for the Microchip Sparx5 SoC.
[all …]
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| /linux/drivers/soc/fsl/ |
| H A D | guts.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
28 /* SoC die attribute definition for QorIQ platform */
31 * Power Architecture-based SoCs T Series
34 /* Die: T4240, SoC: T4240/T4160/T4080 */
39 /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
44 /* Die: T2080, SoC: T2080/T2081 */
49 /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
56 * ARM-based SoCs LS Series
59 /* Die: LS1043A, SoC: LS1043A/LS1023A */
64 /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
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| /linux/drivers/pinctrl/intel/ |
| H A D | pinctrl-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
38 * struct intel_function - Description about a function
48 * struct intel_padgroup - Hardware pad group information
67 * enum - Special treatment for GPIO base in pad group
74 INTEL_GPIO_BASE_ZERO = -2,
75 INTEL_GPIO_BASE_NOMAP = -1,
80 * struct intel_community - Intel pin community description
100 * @pad_map: Optional non-linear mapping of the pads
145 #define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \ argument
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| /linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | keystone-reset.txt | 3 This node is intended to allow SoC reset in case of software reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
31 reset that's triggered by one of WDTs. The list is
33 begins from 0 to 3, as keystone can contain up to 4 SoC
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-dfll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
11 * SoC. These IP blocks together are also known at NVIDIA as
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
25 * variation. In the case of the CPU, it's important to note that the
27 * performance-measurement code and any code that relies on the CPU
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
47 what pinmux functions this SoC supports.
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| /linux/sound/soc/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
25 tristate "SoC I2S Audio support for WM8994 on SMDK"
31 Say Y if you want to add support for SoC audio on the SMDKs.
34 tristate "SoC S/PDIF Audio support for SMDK"
37 Say Y if you want to add support for SoC S/PDIF audio on the SMDK.
40 tristate "SoC PCM Audio support for WM8994 on SMDK"
46 Say Y if you want to add support for SoC audio on the SMDK
119 tristate "SoC I2S Audio support for WM5110 on TM2 board"
126 Say Y if you want to add support for SoC audio on the TM2 board.
129 tristate "SoC I2S Audio support for WM8994 on Aries"
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_util.c | 1 /* SPDX-License-Identifier: MIT */
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
33 const int log_2 = ((x >> 23) & 255) - 128; in _log()
39 in = ((-1.0f / 3) * in + 2) * in - 2.0f / 3; in _log()
189 if (val - floor >= round_pt) in dml_round()
213 return (num + multiple - remainder); in dml_round_to_multiple()
215 return (num - remainder); in dml_round_to_multiple()
222 dml_print("DML: chunk_size = 0x%x\n", rq_regs->chunk_size); in dml_print_data_rq_regs_st()
223 dml_print("DML: min_chunk_size = 0x%x\n", rq_regs->min_chunk_size); in dml_print_data_rq_regs_st()
224 dml_print("DML: meta_chunk_size = 0x%x\n", rq_regs->meta_chunk_size); in dml_print_data_rq_regs_st()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
33 * This file is gcc-parsable HW gospel, coming straight from HW engineers.
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
57 bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in dml_get_voltage_level()
58 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
63 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
64 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
[all …]
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| /linux/Documentation/devicetree/bindings/ptp/ |
| H A D | brcm,ptp-dte.txt | 4 - compatible: should contain the core compatibility string
5 and the SoC compatibility string. The SoC
6 compatibility string is to handle SoC specific
9 "brcm,ptp-dte"
10 SoC compatibility strings:
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
|
| /linux/sound/soc/atmel/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
18 tristate "SoC PCM DAI support for AT91 SSC controller using PDC"
24 in PDC mode configured using audio-graph-card in device-tree.
27 tristate "SoC PCM DAI support for AT91 SSC controller using DMA"
33 in DMA mode configured using audio-graph-card in device-tree.
36 tristate "SoC Audio support for WM8731-based At91sam9g20 evaluation board"
42 Say Y if you want to add support for SoC audio on WM8731-based
56 tristate "SoC Audio support for WM8731-based at91sam9x5 board"
62 Say Y if you want to add support for audio SoC on an
84 tristate "ASoC driver for the Axentia TSE-850"
[all …]
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpc5121-psc.txt | 4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
16 Supported <soc>s: mpc5121, mpc5125
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
[all …]
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| /linux/drivers/pci/controller/ |
| H A D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
45 #include <soc/tegra/cpuidle.h>
46 #include <soc/tegra/pmc.h>
258 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
280 /* used to differentiate between Tegra SoC generations */
354 const struct tegra_pcie_soc *soc; member
380 writel(value, pcie->afi + offset); in afi_writel()
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|