| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 33 * This file is gcc-parsable HW gospel, coming straight from HW engineers.
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
57 bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in dml_get_voltage_level()
58 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
63 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
64 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
66 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
[all …]
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| /linux/drivers/clk/sophgo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for SOPHGO SoC family.
8 This driver supports clock controller of Sophgo CV18XX series SoC.
11 IPs of CV18XX series SoC
18 Sophgo SG2042 SoC. This clock IP uses three oscillators with
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
36 controller on the Sophgo SG2042 SoC.
37 This clock IP depends on SG2042 Clock Generator because it uses
38 clock from Clock Generator IP as input.
46 SoC. This controller requires mulitple PLL clock as input.
[all …]
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| /linux/Documentation/devicetree/bindings/sifive/ |
| H A D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
16 Until these IP blocks (or IP integration) support version
17 auto-discovery, the maintainers of these IP blocks intend to increment
19 interface to these IP blocks changes, or when the functionality of the
20 underlying IP blocks changes in a way that software should be aware of.
[all …]
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| /linux/drivers/usb/dwc3/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
11 USB controller based on the DesignWare USB3 IP Core.
64 AM437x use this IP for USB2/3 functionality.
69 tristate "Samsung Exynos SoC Platform"
75 IP inside, say 'Y' or 'M' if you have one such device.
78 tristate "PCIe-based Platforms"
82 If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 tristate "Synopsys PCIe-based HAPS Platforms"
90 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
117 Support USB2/3 functionality in simple SoC integrations.
[all …]
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| /linux/sound/soc/ti/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
34 Say Y or M here if you want to have support for McASP IP found in
36 - daVinci devices
37 - Sitara line of SoCs (AM335x, AM438x, etc)
38 - OMAP4
39 - DRA7x devices
40 - Keystone devices
41 - K3 devices (am654, j721e)
48 Say Y or M here if you want to have support for DMIC IP found in
56 Say Y or M here if you want to have support for McBSP IP found in
[all …]
|
| /linux/Documentation/devicetree/bindings/display/ |
| H A D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/mediatek/ |
| H A D | mediatek,pwrap.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Flora Fu <flora.fu@mediatek.com>
11 - Alexandre Mergnat <amergnat@baylibre.com>
16 inside the SoC. The communication between the SoC and the PMIC can
20 IP Pairing
22 On MT8135 the pins of some SoC internal peripherals can be on the PMIC.
25 are marked with "IP Pairing". These are optional on SoCs which do not support
[all …]
|
| /linux/drivers/net/can/ctucanfd/ |
| H A D | Kconfig | 2 tristate "CTU CAN-FD IP core" if COMPILE_TEST
4 This driver adds support for the CTU CAN FD open-source IP core.
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
9 Implementation on Intel FPGA-based PCI Express board is available
10 from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
11 on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
15 tristate "CTU CAN-FD IP core PCI/PCIe driver"
19 This driver adds PCI/PCIe support for CTU CAN-FD IP core.
22 at https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd .
25 tristate "CTU CAN-FD IP core platform (FPGA, SoC) driver"
[all …]
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | cdns,macb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
|
| H A D | snps,dwc-qos-ethernet.txt | 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
17 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
[all …]
|
| /linux/Documentation/devicetree/bindings/rtc/ |
| H A D | rtc-omap.txt | 4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
[all …]
|
| /linux/arch/arm/mach-omap2/ |
| H A D | prm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP2+ common Power & Reset Management (PRM) IP block functions
6 * Tero Kristo <t-kristo@ti.com>
24 #include <linux/clk-provider.h>
27 #include "soc.h"
45 * actual amount of memory needed for the SoC
64 /* prm_base: base virtual address of the PRM IP block */
76 * prm_ll_data: function pointers to SoC-specific implementations of
92 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
94 events[i] & prcm_irq_setup->priority_mask[i]; in omap_prcm_events_filter_priority()
[all …]
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
20 pinctrl support completely disabled in this IP block. In Stingray, a
[all …]
|
| /linux/drivers/irqchip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
116 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
125 Enable support for the Broadcom BCM2712 MSI-X target peripheral
126 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
138 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
146 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
205 will be called irq-lan966x-oic.
246 bool "J-Core integrated AIC" if COMPILE_TEST
250 Support for the J-Core integrated AIC.
261 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
[all …]
|
| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
7 signals - can compensate the drift between the two ws signal.
10 internally within the SoC or external components) two sets of bindings is needed:
16 Since the clock instances are part of a single IP this binding is used as a node
17 for the DT clock tree, the IP driver is needed to handle the actual configuration
18 of the IP.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
23 - compatible : shall be "ti,dra7-atl-clock"
[all …]
|
| /linux/Documentation/devicetree/bindings/i2c/ |
| H A D | opencores,i2c-ocores.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
[all …]
|
| /linux/Documentation/devicetree/bindings/media/ |
| H A D | samsung,exynos4210-fimc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-fimc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC Fully Integrated Mobile Camera
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 fimc<n>, where <n> is an integer specifying the IP block instance.
20 - samsung,exynos4210-fimc
21 - samsung,exynos4212-fimc
[all …]
|
| /linux/drivers/usb/musb/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # USB Dual Role (OTG-ready) Controller Drivers
7 # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
14 controller based on the Mentor Graphics silicon IP. Then
19 Texas Instruments families using this IP include DaVinci
22 Allwinner SoCs using this IP include A10, A13, A20, ...
27 module will be called "musb-hdrc".
74 tristate "DA8xx/OMAP-L1x"
115 tristate "Microchip PolarFire SoC platforms"
120 Say Y here to enable support for USB on Microchip's PolarFire SoC.
[all …]
|
| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | brcm,spi-bcm-qspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
18 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
20 io with 3-byte and 4-byte addressing support.
22 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
[all …]
|
| /linux/drivers/phy/realtek/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
15 Enable this to support Realtek SoC USB2 phy transceiver.
17 DWC3 USB IP. This driver will do the PHY initialization
27 Enable this to support Realtek SoC USB3 phy transceiver.
29 DWC3 USB IP. This driver will do the PHY initialization
|
| /linux/Documentation/accel/ |
| H A D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 accelerators in a common way to user-space and provide a common set of
11 These devices can be either stand-alone ASICs or IP blocks inside an SoC/GPU.
13 Machine-Learning (ML) and/or Deep-Learning (DL) computations, the accel layer
19 - Edge AI - doing inference at an edge device. It can be an embedded ASIC/FPGA,
20 or an IP inside a SoC (e.g. laptop web camera). These devices
23 - Inference data-center - single/multi user devices in a large server. This
24 type of device can be stand-alone or an IP inside a SoC or a GPU. It will
25 have on-board DRAM (to hold the DL topology), DMA engines and
26 command submission queues (either kernel or user-space queues).
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 40 dc->ctx->logger
50 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
54 * remain as-is as it provides us with a guarantee from HW that it is correct.
70 * slow-slow corner + 10% margin with voltages aligned to FCLK.
305 input->src.is_hsplit = false; in pipe_ctx_to_e2e_pipe_params()
308 if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || in pipe_ctx_to_e2e_pipe_params()
309 pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { in pipe_ctx_to_e2e_pipe_params()
311 input->src.hsplit_grp = pipe->pipe_idx; in pipe_ctx_to_e2e_pipe_params()
312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) { in pipe_ctx_to_e2e_pipe_params()
313 input->src.is_hsplit = true; in pipe_ctx_to_e2e_pipe_params()
[all …]
|
| /linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
19 3700 SoC.
34 This MSI driver supports Altera MSI to GIC controller IP.
50 system-on-chips, like the Apple M1. This is required for the USB
51 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
107 bool "Cavium Thunder PCIe controller to off-chip devices"
115 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
120 Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
150 in the Intel IXP4xx XScale-based network processor SoC.
186 is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370,
[all …]
|
| /linux/Documentation/userspace-api/media/ |
| H A D | glossary.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
67 :term:`SPI` device, or an :term:`IP Block` inside an
68 :term:`SoC` or :term:`FPGA`.
72 together make a larger user-facing functional peripheral. For
73 instance, the :term:`SoC` :term:`ISP` :term:`IP Block`
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
84 like sub-device hardware components.
[all …]
|
| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
23 connections are fixed for an instance and are dictated by the IP integration
24 into the SoC (excluding the SoCs that have an Interrupt Crossbar or an
25 Interrupt Router IP). Each interrupt line is programmable through a set of
[all …]
|