Lines Matching +full:soc +full:- +full:ip
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
23 connections are fixed for an instance and are dictated by the IP integration
24 into the SoC (excluding the SoCs that have an Interrupt Crossbar or an
25 Interrupt Router IP). Each interrupt line is programmable through a set of
32 registers. All the current OMAP SoCs except for the newest DRA7xx SoC has a
33 single IP instance. DRA7xx has multiple instances with different number of
35 lines can also be routed to different processor sub-systems on DRA7xx as they
38 combine multiple clusters into a single IP block present within the Main
41 output lines of an Interrupt Router. The AM64x SoCS also uses a single IP
48 A Mailbox device node is used to represent a Mailbox IP instance/cluster
49 within a SoC. The sub-mailboxes (actual communication channels) are
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
59 phandle to the intended sub-mailbox child node to be used for communication.
60 The equivalent "mbox-names" property value can be used to give a name to the
64 omap-mbox-descriptor:
65 $ref: /schemas/types.yaml#/definitions/uint32-array
67 The omap-mbox-descriptor is made of up of 3 cells and represents a single
68 uni-directional communication channel. A typical sub-mailbox device uses
69 two such channels - one for transmitting (Tx) and one for receiving (Rx).
71 - description:
72 mailbox fifo id used either for transmitting on ti,mbox-tx channel or
73 for receiving on ti,mbox-rx channel (fifo_id). This is the hardware
75 - description:
81 - description:
86 omap-sub-mailbox:
89 The omap-sub-mailbox is a child node within a Mailbox controller device
96 ti,mbox-tx:
97 $ref: "#/$defs/omap-mbox-descriptor"
98 description: sub-mailbox descriptor property defining a Tx fifo.
100 ti,mbox-rx:
101 $ref: "#/$defs/omap-mbox-descriptor"
102 description: sub-mailbox descriptor property defining a Rx fifo.
104 ti,mbox-send-noirq:
107 Quirk flag to allow the client user of this sub-mailbox to send
109 the Tx ticker. Should be used only on sub-mailboxes used to
113 - ti,mbox-tx
114 - ti,mbox-rx
119 - ti,omap2-mailbox # for OMAP2420, OMAP2430 SoCs
120 - ti,omap3-mailbox # for OMAP3430, OMAP3630 SoCs
121 - ti,omap4-mailbox # for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs
122 - ti,am654-mailbox # for K3 AM65x, J721E and J7200 SoCs
123 - ti,am64-mailbox # for K3 AM64x SoCs
133 ti,mbox-num-users property, but is usually limited by the number of
134 interrupts reaching the main processor. An interrupt-parent property
138 "#mbox-cells":
141 The specifier is a phandle to an omap-sub-mailbox device.
143 ti,mbox-num-users:
149 ti,mbox-num-fifos:
151 description: Number of h/w fifo queues within the mailbox IP block.
166 "^mbox-[a-z0-9-]+$":
167 $ref: "#/$defs/omap-sub-mailbox"
170 - compatible
171 - reg
172 - interrupts
173 - "#mbox-cells"
174 - ti,mbox-num-users
175 - ti,mbox-num-fifos
178 - if:
182 - ti,am654-mailbox
183 - ti,am64-mailbox
186 ti,mbox-num-users:
188 ti,mbox-num-fifos:
194 - if:
198 - ti,omap4-mailbox
201 ti,mbox-num-users:
203 ti,mbox-num-fifos:
209 - if:
213 - ti,omap3-mailbox
216 ti,mbox-num-users:
218 ti,mbox-num-fifos:
224 - if:
228 - ti,omap2-mailbox
231 ti,mbox-num-users:
233 ti,mbox-num-fifos:
242 - |
244 #include <dt-bindings/interrupt-controller/arm-gic.h>
246 compatible = "ti,omap4-mailbox";
249 #mbox-cells = <1>;
250 ti,mbox-num-users = <3>;
251 ti,mbox-num-fifos = <8>;
253 mbox_ipu: mbox-ipu {
254 ti,mbox-tx = <0 0 0>;
255 ti,mbox-rx = <1 0 0>;
257 mbox_dsp: mbox-dsp {
258 ti,mbox-tx = <3 0 0>;
259 ti,mbox-rx = <2 0 0>;
263 - |
266 compatible = "ti,omap4-mailbox";
269 #mbox-cells = <1>;
270 ti,mbox-num-users = <4>;
271 ti,mbox-num-fifos = <8>;
273 mbox_wkupm3: mbox-wkup-m3 {
274 ti,mbox-tx = <0 0 0>;
275 ti,mbox-rx = <0 0 3>;
276 ti,mbox-send-noirq;
280 - |
283 compatible = "ti,am654-mailbox";
285 #mbox-cells = <1>;
286 ti,mbox-num-users = <4>;
287 ti,mbox-num-fifos = <16>;
288 interrupt-parent = <&intr_main_navss>;
291 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
292 ti,mbox-tx = <1 0 0>;
293 ti,mbox-rx = <0 0 0>;