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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sar2130p-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SAR2130P TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC.
20 const: qcom,sar2130p-tlmm
38 - $ref: "#/$defs/qcom-sar2130p-tlmm-state"
41 $ref: "#/$defs/qcom-sar2130p-tlmm-state"
45 qcom-sar2130p-tlmm-state:
110 compatible = "qcom,sar2130p-tlmm";
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sar2130p-gcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
7 title: Qualcomm Global Clock & Reset Controller on sar2130p
14 power domains on sar2130p.
16 See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
20 const: qcom,sar2130p-gcc
52 compatible = "qcom,sar2130p-gcc";
H A Dqcom,sm8450-gpucc.yaml17 include/dt-bindings/clock/qcom,sar2130p-gpucc.h
28 - qcom,sar2130p-gpucc
H A Dqcom,sm8550-tcsr.yaml24 - qcom,sar2130p-tcsr
H A Dqcom,rpmhcc.yaml22 - qcom,sar2130p-rpmh-clk
H A Dqcom,sm8550-dispcc.yaml25 - qcom,sar2130p-dispcc
/linux/drivers/clk/qcom/
H A Dgpucc-sar2130p.c13 #include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
14 #include <dt-bindings/reset/qcom,sar2130p-gpucc.h>
469 { .compatible = "qcom,sar2130p-gpucc" },
495 .name = "gpu_cc-sar2130p",
501 MODULE_DESCRIPTION("QTI GPU_CC SAR2130P Driver");
H A DMakefile90 obj-$(CONFIG_SAR_GCC_2130P) += gcc-sar2130p.o
91 obj-$(CONFIG_SAR_GPUCC_2130P) += gpucc-sar2130p.o
H A DKconfig587 tristate "SAR2130P Global Clock Controller"
591 Support for the global clock controller on SAR2130P devices.
596 tristate "SAR2130P Graphics clock controller"
600 Support for the graphics clock controller on SAR2130P devices.
1021 SAR2130P, SM8550 or SM8650 devices.
H A Dtcsrcc-sm8550.c169 { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc },
H A Dgcc-sar2130p.c13 #include <dt-bindings/clock/qcom,sar2130p-gcc.h>
2314 { .compatible = "qcom,sar2130p-gcc" },
2348 .name = "gcc-sar2130p",
2365 MODULE_DESCRIPTION("QTI GCC SAR2130P Driver");
H A Ddispcc-sm8550.c1760 { .compatible = "qcom,sar2130p-dispcc" },
1791 } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) { in disp_cc_sm8550_probe()
H A Dclk-rpmh.c895 { .compatible = "qcom,sar2130p-rpmh-clk", .data = &clk_rpmh_sar2130p},
/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom-ipcc.yaml31 - qcom,sar2130p-ipcc
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dqcom,pdc.yaml32 - qcom,sar2130p-pdc
/linux/drivers/pinctrl/qcom/
H A DKconfig.msm231 tristate "Qualcomm Technologies Inc SAR2130P pin controller driver"
236 Technologies Inc SAR2130P platform.
H A DMakefile38 obj-$(CONFIG_PINCTRL_SAR2130P) += pinctrl-sar2130p.o
H A Dpinctrl-sar2130p.c1478 { .compatible = "qcom,sar2130p-tlmm", .data = &sar2130p_tlmm},
1485 .name = "sar2130p-tlmm",
1504 MODULE_DESCRIPTION("QTI SAR2130P TLMM driver");
/linux/drivers/pmdomain/qcom/
H A Drpmhpd.c262 /* SAR2130P RPMH powerdomains */
717 { .compatible = "qcom,sar2130p-rpmhpd", .data = &sar2130p_desc},
/linux/drivers/soc/qcom/
H A Dsocinfo.c425 { qcom_board_id(SAR2130P) },
H A Dllcc-qcom.c4037 { .compatible = "qcom,sar2130p-llcc", .data = &sar2130p_cfgs },