163f4e4b6SKonrad Dybcio# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 263f4e4b6SKonrad Dybcio%YAML 1.2 363f4e4b6SKonrad Dybcio--- 463f4e4b6SKonrad Dybcio$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml# 563f4e4b6SKonrad Dybcio$schema: http://devicetree.org/meta-schemas/core.yaml# 663f4e4b6SKonrad Dybcio 763f4e4b6SKonrad Dybciotitle: Qualcomm Graphics Clock & Reset Controller on SM8450 863f4e4b6SKonrad Dybcio 963f4e4b6SKonrad Dybciomaintainers: 10*0710c3d3SKonrad Dybcio - Konrad Dybcio <konradybcio@kernel.org> 1163f4e4b6SKonrad Dybcio 1263f4e4b6SKonrad Dybciodescription: | 1363f4e4b6SKonrad Dybcio Qualcomm graphics clock control module provides the clocks, resets and power 1463f4e4b6SKonrad Dybcio domains on Qualcomm SoCs. 1563f4e4b6SKonrad Dybcio 1663f4e4b6SKonrad Dybcio See also:: 1763f4e4b6SKonrad Dybcio include/dt-bindings/clock/qcom,sm4450-gpucc.h 18778af143SJagadeesh Kona include/dt-bindings/clock/qcom,sm8450-gpucc.h 1963f4e4b6SKonrad Dybcio include/dt-bindings/clock/qcom,sm8550-gpucc.h 20a0aa7fa5SNeil Armstrong include/dt-bindings/reset/qcom,sm8450-gpucc.h 21bb213e13SRajendra Nayak include/dt-bindings/reset/qcom,sm8650-gpucc.h 2263f4e4b6SKonrad Dybcio include/dt-bindings/reset/qcom,x1e80100-gpucc.h 2363f4e4b6SKonrad Dybcio 2463f4e4b6SKonrad Dybcioproperties: 2563f4e4b6SKonrad Dybcio compatible: 2663f4e4b6SKonrad Dybcio enum: 27778af143SJagadeesh Kona - qcom,sm4450-gpucc 28a0aa7fa5SNeil Armstrong - qcom,sm8450-gpucc 29bb213e13SRajendra Nayak - qcom,sm8550-gpucc 3063f4e4b6SKonrad Dybcio - qcom,sm8650-gpucc 3163f4e4b6SKonrad Dybcio - qcom,x1e80100-gpucc 3263f4e4b6SKonrad Dybcio 3363f4e4b6SKonrad Dybcio clocks: 3463f4e4b6SKonrad Dybcio items: 3563f4e4b6SKonrad Dybcio - description: Board XO source 3663f4e4b6SKonrad Dybcio - description: GPLL0 main branch source 3763f4e4b6SKonrad Dybcio - description: GPLL0 div branch source 3863f4e4b6SKonrad Dybcio 3963f4e4b6SKonrad Dybciorequired: 4063f4e4b6SKonrad Dybcio - compatible 4163f4e4b6SKonrad Dybcio - clocks 427e828d77SKrzysztof Kozlowski - '#power-domain-cells' 437e828d77SKrzysztof Kozlowski 447e828d77SKrzysztof KozlowskiallOf: 457e828d77SKrzysztof Kozlowski - $ref: qcom,gcc.yaml# 4663f4e4b6SKonrad Dybcio 4763f4e4b6SKonrad DybciounevaluatedProperties: false 4863f4e4b6SKonrad Dybcio 4963f4e4b6SKonrad Dybcioexamples: 5063f4e4b6SKonrad Dybcio - | 5163f4e4b6SKonrad Dybcio #include <dt-bindings/clock/qcom,gcc-sm8450.h> 5263f4e4b6SKonrad Dybcio #include <dt-bindings/clock/qcom,rpmh.h> 5363f4e4b6SKonrad Dybcio 5463f4e4b6SKonrad Dybcio soc { 5563f4e4b6SKonrad Dybcio #address-cells = <2>; 5663f4e4b6SKonrad Dybcio #size-cells = <2>; 5763f4e4b6SKonrad Dybcio 5863f4e4b6SKonrad Dybcio clock-controller@3d90000 { 5963f4e4b6SKonrad Dybcio compatible = "qcom,sm8450-gpucc"; 6063f4e4b6SKonrad Dybcio reg = <0 0x03d90000 0 0xa000>; 6163f4e4b6SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 6263f4e4b6SKonrad Dybcio <&gcc GCC_GPU_GPLL0_CLK_SRC>, 6363f4e4b6SKonrad Dybcio <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 6463f4e4b6SKonrad Dybcio #clock-cells = <1>; 6563f4e4b6SKonrad Dybcio #reset-cells = <1>; 6663f4e4b6SKonrad Dybcio #power-domain-cells = <1>; 6763f4e4b6SKonrad Dybcio }; 68 }; 69... 70