| /freebsd/sys/dev/uart/ |
| H A D | uart_bus_acpi.c | 85 uint32_t rclk; in uart_acpi_probe() local
89 rclk = 0; in uart_acpi_probe()
99 size = device_get_property(dev, "clock-frequency", &rclk, in uart_acpi_probe()
100 sizeof(rclk), DEVICE_PROP_UINT32); in uart_acpi_probe()
101 if (size < 0 || rclk == 0) in uart_acpi_probe()
102 rclk = cd->cd_rclk; in uart_acpi_probe()
105 rclk, 0, 0, cd->cd_quirks)); in uart_acpi_probe()
|
| H A D | uart_bus_puc.c | 69 uintptr_t rclk, type; in uart_puc_probe() local
81 if (BUS_READ_IVAR(parent, dev, PUC_IVAR_CLOCK, &rclk)) in uart_puc_probe()
82 rclk = 0; in uart_puc_probe()
83 return (uart_bus_probe(dev, 0, 0, rclk, 0, 0, 0)); in uart_puc_probe()
|
| H A D | uart_cpu_acpi.c | 78 di->bas.rclk = 0; in uart_cpu_acpi_init_devinfo()
203 * Rev 3 and newer can specify a rclk, use it if it's there. It's in uart_cpu_acpi_spcr()
204 * defined to be 0 when it's not known, and we've initialized rclk to 0 in uart_cpu_acpi_spcr()
208 di->bas.rclk = spcr->UartClkFreq; in uart_cpu_acpi_spcr()
211 * If no rclk is set, then we will assume the BIOS has configured the in uart_cpu_acpi_spcr()
212 * hardware at the stated baudrate, so we can use it to guess the rclk in uart_cpu_acpi_spcr()
215 if (di->bas.rclk == 0) in uart_cpu_acpi_spcr()
|
| H A D | uart_cpu_fdt.c | 78 u_int shift, iowidth, rclk; in uart_cpu_getdev() local
87 err = uart_cpu_fdt_probe(&class, &bst, &bsh, &br, &rclk, in uart_cpu_getdev()
99 di->bas.rclk = rclk; in uart_cpu_getdev()
|
| H A D | uart_cpu_arm64.c | 85 u_int rclk, shift, iowidth; in uart_cpu_fdt_setup() local
88 err = uart_cpu_fdt_probe(&class, &bst, &bsh, &br, &rclk, in uart_cpu_fdt_setup()
100 di->bas.rclk = rclk; in uart_cpu_fdt_setup()
|
| H A D | uart.h | 36 * to access the UART. The rclk field, although not important to actually
44 u_int rclk; member
48 u_int rclk_guess;/* if rclk == 0, use baud + divisor to compute rclk */
|
| H A D | uart_dev_msm.c | 150 if (bas->rclk == 0) in msm_init()
151 bas->rclk = DEF_CLK; in msm_init()
153 KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk")); in msm_init()
437 if (sc->sc_bas.rclk == 0) in msm_bus_param()
438 sc->sc_bas.rclk = DEF_CLK; in msm_bus_param()
440 KASSERT(sc->sc_bas.rclk != 0, ("msm_init: Invalid rclk")); in msm_bus_param()
|
| H A D | uart_dev_ns8250.c | 160 return (16000000 * divisor / bas->rclk); in ns8250_delay()
161 return (16000 * divisor / (bas->rclk / 1000)); in ns8250_delay()
165 ns8250_divisor(int rclk, int baudrate) in ns8250_divisor() argument
173 divisor = (rclk / (baudrate << 3) + 1) >> 1; in ns8250_divisor()
176 actual_baud = rclk / (divisor << 4); in ns8250_divisor()
302 /* Set baudrate if we know a rclk and both are not 0. */ in ns8250_param()
303 if (baudrate > 0 && bas->rclk > 0) { in ns8250_param()
304 divisor = ns8250_divisor(bas->rclk, baudrate); in ns8250_param()
378 * Loader tells us to infer the rclk when it sets xo to 0 in in ns8250_init()
380 * calculate rclk from baudrate and the divisor register. If 'div' is in ns8250_init()
[all …]
|
| H A D | uart_core.c | 495 uart_bus_probe(device_t dev, int regshft, int regiowidth, int rclk, int rid, int chan, int quirks) in uart_bus_probe() argument
554 sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk; in uart_bus_probe()
562 if (sysdev->bas.rclk != 0) { in uart_bus_probe()
564 sc->sc_bas.rclk = sysdev->bas.rclk; in uart_bus_probe()
567 sysdev->bas.rclk = sc->sc_bas.rclk; in uart_bus_probe()
757 "rclk", CTLFLAG_RD, &sc->sc_bas.rclk, 0, in uart_bus_attach()
|
| H A D | uart_dev_pl011.c | 241 if (bas->rclk != 0 && baudrate != 0) { in uart_pl011_param()
242 baud = bas->rclk * 4 / baudrate; in uart_pl011_param()
257 * Loader tells us to infer the rclk when it sets xo to 0 in in uart_pl011_param()
259 * baudrate was set by the firmware, so calculate rclk from baudrate and in uart_pl011_param()
261 * will have us fall back to other rclk methods. This method should be in uart_pl011_param()
265 if (bas->rclk == 0 && baudrate > 0 && bas->rclk_guess) { in uart_pl011_param()
270 bas->rclk = (div * baudrate) / 4; in uart_pl011_param()
|
| H A D | uart_bus_pci.c | 73 int rclk; member
271 sysdev->bas.rclk = sc->sc_bas.rclk; in uart_pci_unique_console_match()
283 .rclk = 0, in uart_pci_probe()
299 /* XXX rclk what to do */ in uart_pci_probe()
308 result = uart_bus_probe(dev, id->regshft, 0, id->rclk, in uart_pci_probe()
|
| H A D | uart_cpu_powerpc.c | 188 if (OF_getprop(input, "clock-frequency", &di->bas.rclk, in uart_cpu_getdev()
189 sizeof(di->bas.rclk)) == -1) in uart_cpu_getdev()
190 di->bas.rclk = 230400; in uart_cpu_getdev()
|
| H A D | uart_dev_mvebu.c | 152 uart_mvebu_divisor(int rclk, int baudrate) in uart_mvebu_divisor() argument
159 divisor = (rclk >> 4) / baudrate; in uart_mvebu_divisor()
199 divisor = uart_mvebu_divisor(bas->rclk, baudrate); in uart_mvebu_param()
225 bas->rclk = DEFAULT_RCLK; in uart_mvebu_init()
418 baudrate = bas->rclk/(divisor * 16); in uart_mvebu_bus_ioctl()
|
| H A D | uart_dev_imx.c | 133 rate = bas->rclk / predivs[i]; in imx_uart_getbaud()
201 if ((baudrate > 0) && (bas->rclk != 0)) { in imx_uart_init()
202 baseclk = bas->rclk; in imx_uart_init()
361 bas->rclk = (uint32_t)freq; in imx_uart_setup_clocks()
380 bas->rclk = imx_ccm_uart_hz(); in imx_uart_bus_attach()
|
| H A D | uart_subr.c | 228 di->bas.rclk = 0; in uart_getenv()
274 di->bas.rclk = uart_parse_long(&spec); in uart_getenv()
275 if (di->bas.rclk == 0) in uart_getenv()
|
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | qcom,sdx75-gcc.yaml | 27 - description: EMAC0 sgmiiphy mac rclk source
29 - description: EMAC0 sgmiiphy rclk source
31 - description: EMAC1 sgmiiphy mac rclk source
33 - description: EMAC1 sgmiiphy rclk source
|
| H A D | baikal,bt1-ccu-pll.yaml | 64 Rclk-+->+---+ | |
70 where Rclk is the reference clock coming from XTAL, NR - reference clock
|
| /freebsd/sys/dev/scc/ |
| H A D | scc_bfe_quicc.c | 49 uintptr_t devtype, rclk; in scc_quicc_probe() local
64 if (BUS_READ_IVAR(parent, dev, QUICC_IVAR_BRGCLK, &rclk)) in scc_quicc_probe()
65 rclk = 0; in scc_quicc_probe()
66 return (scc_bfe_probe(dev, 0, rclk, 0)); in scc_quicc_probe()
|
| H A D | scc_bfe.h | 36 * to access the SCC. The rclk field, although not important to actually
44 u_int rclk; member
142 int scc_bfe_probe(device_t dev, u_int regshft, u_int rclk, u_int rid);
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ftgmac100.txt | 29 IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The
34 - "RCLK": Clock gate for the RMII RCLK
|
| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | msm8992-pins.dtsi | 33 /* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */
83 sdc1_rclk_on: rclk-on {
87 sdc1_rclk_off: rclk-off {
|
| /freebsd/sys/contrib/device-tree/src/arm/aspeed/ |
| H A D | aspeed-bmc-portwell-neptune.dts | 85 clock-names = "MACCLK", "RCLK";
94 clock-names = "MACCLK", "RCLK";
|
| /freebsd/sys/riscv/sifive/ |
| H A D | sifive_uart.c | 217 bas->rclk = freq; in sfuart_bus_attach()
343 *(int*)data = bas->rclk / (reg + 1); in sfuart_bus_ioctl()
414 if (baudrate > 0 && bas->rclk != 0) { in sfuart_bus_param()
415 reg = (bas->rclk / baudrate) - 1; in sfuart_bus_param()
|
| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | sdhci-msm.txt | 54 "cal" - reference clock for RCLK delay calibration (optional)
55 "sleep" - sleep clock for RCLK delay calibration (optional)
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | fsl,qe-tsa.yaml | 76 - const: rclk
195 clock-names = "rsync", "rclk";
|