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/linux/drivers/clk/qcom/
H A Dclk-regmap.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
14 * clk_is_enabled_regmap - standard is_enabled() for regmap users
24 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_is_enabled_regmap() local
28 ret = regmap_read(rclk->regmap, rclk->enable_reg, &val); in clk_is_enabled_regmap()
32 if (rclk->enable_is_inverted) in clk_is_enabled_regmap()
33 return (val & rclk->enable_mask) == 0; in clk_is_enabled_regmap()
35 return (val & rclk->enable_mask) != 0; in clk_is_enabled_regmap()
40 * clk_enable_regmap - standard enable() for regmap users
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H A Dclk-regmap.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
12 * struct clk_regmap - regmap supporting clock
13 * @hw: handle between common and hardware-specific interfaces
36 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
/linux/sound/soc/samsung/
H A Darndale.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <sound/soc-dapm.h>
27 unsigned long rclk; in arndale_rt5631_hw_params() local
31 rclk = params_rate(params) * rfs; in arndale_rt5631_hw_params()
44 ret = snd_soc_dai_set_sysclk(codec_dai, 0, rclk, SND_SOC_CLOCK_OUT); in arndale_rt5631_hw_params()
60 unsigned int rfs, rclk; in arndale_wm1811_hw_params() local
70 rclk = params_rate(params) * rfs; in arndale_wm1811_hw_params()
75 * samsung/clk-exynos5250.c for list of available EPLL rates). in arndale_wm1811_hw_params()
80 rclk + 1, SND_SOC_CLOCK_IN); in arndale_wm1811_hw_params()
89 DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5631-aif1")),
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H A Dsnow.c1 // SPDX-License-Identifier: GPL-2.0
33 struct snow_priv *priv = snd_soc_card_get_drvdata(rtd->card); in snow_card_hw_params()
35 unsigned long int rclk; in snow_card_hw_params() local
36 long int freq = -EINVAL; in snow_card_hw_params()
41 dev_err(rtd->card->dev, "Invalid bit-width: %d\n", bitwidth); in snow_card_hw_params()
46 dev_err(rtd->card->dev, "Unsupported bit-width: %d\n", bitwidth); in snow_card_hw_params()
47 return -EINVAL; in snow_card_hw_params()
72 return -EINVAL; in snow_card_hw_params()
75 rclk = params_rate(params) * rfs; in snow_card_hw_params()
79 if ((pll_rate[i] - rclk * psr) <= 2) { in snow_card_hw_params()
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sdx75-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Imran Shaik <quic_imrashai@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
17 See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
21 const: qcom,sdx75-gcc
25 - description: Board XO source
26 - description: Sleep clock source
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H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c1 // SPDX-License-Identifier: GPL-2.0
16 * enum ice_dpll_pin_type - enumerate ice pin types:
32 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
40 * ice_dpll_is_reset - check if reset is in progress
47 * * false - no reset in progress
48 * * true - reset in progress
52 if (ice_is_reset_in_progress(pf->state)) { in ice_dpll_is_reset()
60 * ice_dpll_pin_freq_set - set pin's frequency
69 * Context: Called under pf->dplls.lock
71 * * 0 - success
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H A Dice_dpll.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /** ice_dpll_pin - store info about pins
37 /** ice_dpll - store info required for DPLL control
71 /** ice_dplls - store info required for CCU (clock controlling unit)
79 * @rclk: recovered pins pointer
96 struct ice_dpll_pin rclk; member
/linux/drivers/slimbus/
H A Dqcom-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
88 /* Resource group info for manager, and non-ported generic device-components */
116 struct clk *rclk; member
125 __iowrite32_copy(ctrl->base + tx_reg, buf, count); in qcom_slim_queue_tx()
136 spin_lock_irqsave(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
137 if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { in slim_alloc_rxbuf()
138 spin_unlock_irqrestore(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
139 dev_err(ctrl->dev, "RX QUEUE full!"); in slim_alloc_rxbuf()
142 idx = ctrl->rx.tail; in slim_alloc_rxbuf()
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/linux/Documentation/devicetree/bindings/net/
H A Dfaraday,ftgmac100.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Po-Yu Chuang <ratbert@faraday-tech.com>
18 - const: faraday,ftgmac100
19 - items:
20 - enum:
21 - aspeed,ast2400-mac
22 - aspeed,ast2500-mac
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/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-portwell-neptune.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "portwell,neptune-bmc", "aspeed,ast2500";
16 stdout-path = &uart5;
25 compatible = "gpio-leds";
29 default-state = "on";
34 linux,default-trigger = "heartbeat";
40 // postcode3-7 are GPIOH3-H7
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H A Daspeed-bmc-facebook-yamp.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,yamp-bmc", "aspeed,ast2500";
23 stdout-path = &uart5;
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_txd2_default
37 use-ncsi;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_rmii1_default>;
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H A Daspeed-bmc-supermicro-x11spi.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
10 compatible = "supermicro,x11spi-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
32 iio-hwmon {
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H A Daspeed-bmc-intel-s2600wf.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
9 compatible = "intel,s2600wf-bmc", "aspeed,ast2500";
12 stdout-path = &uart5;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
26 no-map;
31 iio-hwmon {
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H A Daspeed-bmc-inspur-on5263m5.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "inspur,on5263m5-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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/linux/include/dt-bindings/sound/
H A Dsamsung-i2s.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock
/linux/drivers/clk/
H A Dclk-ast2600.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
14 #include <dt-bindings/clock/ast2600-clock.h>
16 #include "clk-aspeed.h"
20 * explicitly-configured clocks (ASPEED_CLK_HPLL and up).
94 * handled by using -1 as the index for the reset, and the consumer must
104 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
105 [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
106 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
107 /* vclk parent - dclk/d1clk/hclk/mclk */
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H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp418.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
11 #include "ipq9574-rdp-common.dtsi"
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
15 compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
20 pinctrl-0 = <&sdc_default_state>;
21 pinctrl-names = "default";
22 mmc-ddr-1_8v;
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H A Dipq9574-rdp433.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 /dts-v1/;
11 #include "ipq9574-rdp-common.dtsi"
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
15 compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
19 pinctrl-0 = <&sdc_default_state>;
20 pinctrl-names = "default";
21 mmc-ddr-1_8v;
22 mmc-hs200-1_8v;
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H A Dqcs404-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
19 stdout-path = "serial0";
22 vph_pwr: vph-pwr-regulator {
23 compatible = "regulator-fixed";
24 regulator-name = "vph_pwr";
25 regulator-always-on;
26 regulator-boot-on;
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/linux/drivers/clk/renesas/
H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
39 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
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/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
12 #include <linux/dma-mapping.h>
54 /* For NC-SI to register a fixed-link phy device */
103 struct clk *rclk; member
126 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
130 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
132 priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
136 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
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/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
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