Lines Matching +full:rclk +full:- +full:- +full:- +full:- +full:-
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
14 #include <dt-bindings/clock/ast2600-clock.h>
16 #include "clk-aspeed.h"
20 * explicitly-configured clocks (ASPEED_CLK_HPLL and up).
94 * handled by using -1 as the index for the reset, and the consumer must
104 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
105 [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
106 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
107 /* vclk parent - dclk/d1clk/hclk/mclk */
108 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
109 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
111 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
112 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
113 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
115 …[ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 e…
117 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
119 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
120 …[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port…
121 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
123 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
124 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
126 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
127 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
129 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
131 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
132 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
133 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
135 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
136 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
139 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", "i3cclk", 0 }, /* I3C0 */
140 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", "i3cclk", 0 }, /* I3C1 */
141 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", "i3cclk", 0 }, /* I3C2 */
142 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", "i3cclk", 0 }, /* I3C3 */
143 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", "i3cclk", 0 }, /* I3C4 */
144 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", "i3cclk", 0 }, /* I3C5 */
146 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
147 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
148 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
149 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
150 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
151 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
152 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
153 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
154 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
155 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
156 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
157 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
158 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
159 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
160 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", "fsiclk", 0 }, /* FSI */
253 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ in ast2600_calc_apll()
258 mult = (2 - od) * (m + 2); in ast2600_calc_apll()
273 if (gate->reset_idx < 32) in get_reset_reg()
281 if (gate->clock_idx < 32) in get_clock_reg()
290 u32 clk = get_bit(gate->clock_idx); in aspeed_g6_clk_is_enabled()
291 u32 rst = get_bit(gate->reset_idx); in aspeed_g6_clk_is_enabled()
301 if (gate->reset_idx >= 0) { in aspeed_g6_clk_is_enabled()
302 regmap_read(gate->map, get_reset_reg(gate), ®); in aspeed_g6_clk_is_enabled()
308 regmap_read(gate->map, get_clock_reg(gate), ®); in aspeed_g6_clk_is_enabled()
310 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; in aspeed_g6_clk_is_enabled()
319 u32 clk = get_bit(gate->clock_idx); in aspeed_g6_clk_enable()
320 u32 rst = get_bit(gate->reset_idx); in aspeed_g6_clk_enable()
322 spin_lock_irqsave(gate->lock, flags); in aspeed_g6_clk_enable()
325 spin_unlock_irqrestore(gate->lock, flags); in aspeed_g6_clk_enable()
329 if (gate->reset_idx >= 0) { in aspeed_g6_clk_enable()
331 regmap_write(gate->map, get_reset_reg(gate), rst); in aspeed_g6_clk_enable()
337 if (gate->flags & CLK_GATE_SET_TO_DISABLE) { in aspeed_g6_clk_enable()
339 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk); in aspeed_g6_clk_enable()
342 regmap_write(gate->map, get_clock_reg(gate), clk); in aspeed_g6_clk_enable()
345 if (gate->reset_idx >= 0) { in aspeed_g6_clk_enable()
349 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst); in aspeed_g6_clk_enable()
352 spin_unlock_irqrestore(gate->lock, flags); in aspeed_g6_clk_enable()
361 u32 clk = get_bit(gate->clock_idx); in aspeed_g6_clk_disable()
363 spin_lock_irqsave(gate->lock, flags); in aspeed_g6_clk_disable()
365 if (gate->flags & CLK_GATE_SET_TO_DISABLE) { in aspeed_g6_clk_disable()
366 regmap_write(gate->map, get_clock_reg(gate), clk); in aspeed_g6_clk_disable()
369 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk); in aspeed_g6_clk_disable()
372 spin_unlock_irqrestore(gate->lock, flags); in aspeed_g6_clk_disable()
389 return regmap_write(ar->map, reg + 0x04, rst); in aspeed_g6_reset_deassert()
399 return regmap_write(ar->map, reg, rst); in aspeed_g6_reset_assert()
411 ret = regmap_read(ar->map, reg, &val); in aspeed_g6_reset_status()
436 return ERR_PTR(-ENOMEM); in aspeed_g6_clk_hw_register_gate()
444 gate->map = map; in aspeed_g6_clk_hw_register_gate()
445 gate->clock_idx = clock_idx; in aspeed_g6_clk_hw_register_gate()
446 gate->reset_idx = reset_idx; in aspeed_g6_clk_hw_register_gate()
447 gate->flags = clk_gate_flags; in aspeed_g6_clk_hw_register_gate()
448 gate->lock = lock; in aspeed_g6_clk_hw_register_gate()
449 gate->hw.init = &init; in aspeed_g6_clk_hw_register_gate()
451 hw = &gate->hw; in aspeed_g6_clk_hw_register_gate()
476 "usb-phy-40m",
483 struct device *dev = &pdev->dev; in aspeed_g6_clk_probe()
490 map = syscon_node_to_regmap(dev->of_node); in aspeed_g6_clk_probe()
498 return -ENOMEM; in aspeed_g6_clk_probe()
500 ar->map = map; in aspeed_g6_clk_probe()
502 ar->rcdev.owner = THIS_MODULE; in aspeed_g6_clk_probe()
503 ar->rcdev.nr_resets = 64; in aspeed_g6_clk_probe()
504 ar->rcdev.ops = &aspeed_g6_reset_ops; in aspeed_g6_clk_probe()
505 ar->rcdev.of_node = dev->of_node; in aspeed_g6_clk_probe()
507 ret = devm_reset_controller_register(dev, &ar->rcdev); in aspeed_g6_clk_probe()
522 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw; in aspeed_g6_clk_probe()
533 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw; in aspeed_g6_clk_probe()
563 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; in aspeed_g6_clk_probe()
577 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; in aspeed_g6_clk_probe()
579 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
591 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw; in aspeed_g6_clk_probe()
593 /* RMII1 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
599 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; in aspeed_g6_clk_probe()
601 /* RMII2 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
607 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; in aspeed_g6_clk_probe()
609 /* MAC1/2 RMII 50MHz RCLK */ in aspeed_g6_clk_probe()
621 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw; in aspeed_g6_clk_probe()
623 /* RMII3 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
629 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw; in aspeed_g6_clk_probe()
631 /* RMII4 50MHz (RCLK) output enable */ in aspeed_g6_clk_probe()
637 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw; in aspeed_g6_clk_probe()
646 aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw; in aspeed_g6_clk_probe()
657 aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw; in aspeed_g6_clk_probe()
659 /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */ in aspeed_g6_clk_probe()
662 /* P-Bus (BCLK) clock divider */ in aspeed_g6_clk_probe()
669 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw; in aspeed_g6_clk_probe()
678 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw; in aspeed_g6_clk_probe()
687 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw; in aspeed_g6_clk_probe()
693 if (!gd->name) in aspeed_g6_clk_probe()
700 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; in aspeed_g6_clk_probe()
702 gd->name, in aspeed_g6_clk_probe()
703 gd->parent_name, in aspeed_g6_clk_probe()
704 gd->flags, in aspeed_g6_clk_probe()
706 gd->clock_idx, in aspeed_g6_clk_probe()
707 gd->reset_idx, in aspeed_g6_clk_probe()
712 aspeed_g6_clk_data->hws[i] = hw; in aspeed_g6_clk_probe()
719 { .compatible = "aspeed,ast2600-scu" },
726 .name = "ast2600-clk",
757 * High-speed PLL clock derived from the crystal. This the CPU clock, in aspeed_g6_cc()
761 aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val); in aspeed_g6_cc()
764 aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val); in aspeed_g6_cc()
767 aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val); in aspeed_g6_cc()
770 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val); in aspeed_g6_cc()
773 aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val); in aspeed_g6_cc()
799 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw; in aspeed_g6_cc()
805 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw; in aspeed_g6_cc()
811 aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw; in aspeed_g6_cc()
814 hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000); in aspeed_g6_cc()
815 aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw; in aspeed_g6_cc()
823 aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw; in aspeed_g6_cc()
826 aspeed_g6_clk_data->hws[ASPEED_CLK_FSI] = hw; in aspeed_g6_cc()
845 aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS; in aspeed_g6_cc_init()
852 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); in aspeed_g6_cc_init()
856 * but as this is an MMIO-backed regmap, subsequent regmap in aspeed_g6_cc_init()
871 CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);