| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | rockchip,i2s-tdm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
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| H A D | allwinner,sun4i-a10-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#sound-dai-cells":
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
21 - const: allwinner,sun8i-a83t-i2s
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| /freebsd/sys/contrib/ncsw/inc/flib/ |
| H A D | fsl_fman_port.h | 2 * Copyright 2008-2013 Freescale Semiconductor Inc.
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
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| /freebsd/sys/contrib/dev/athk/ath10k/ |
| H A D | rx_desc.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
55 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
56 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
57 * 0. The PPDU start status will only be valid when this bit
62 * PPDU end status will only be valid when this bit is set.
65 * Multicast / broadcast indicator. Only set when the MAC
67 * matches one of the 4 BSSID registers. Only set when
72 * count. Only set when first_msdu is set.
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| /freebsd/crypto/openssl/doc/designs/quic-design/ |
| H A D | connection-state-machine.md | 5 ---------
7 QUIC client-side connection state can be broken down into five coarse phases of
10 - The Idle substate (which is simply the state before we have started trying to
12 - The Active state, which comprises two substates:
13 - The Establishing state, which comprises many different substates;
14 - The Open state;
15 - The Terminating state, which comprises several substates;
16 - The Terminated state, which is the terminal state.
22 concepts. For example, the Establishing state uses Initial, Handshake and 1-RTT
25 This discussion is (currently) given from the client side perspective only.
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| H A D | quic-fc.md | 5 ---------------------------------
8 transmission of stream data could be prevented by connection-level flow control,
9 by stream-level flow control, or both. Flow control uses a credit-based model in
14 It is important to note that both connection and stream-level flow control
15 relate only to the transmission of QUIC stream data. QUIC flow control at stream
18 again, this still only counts as one byte for the purposes of flow control. Note
32 Connection-level flow control is controlled by the `MAX_DATA` frame;
33 stream-level flow control is controlled by the `MAX_STREAM_DATA` frame.
38 our connection-level credit, and a conformant QUIC implementation can choose to
43 Note that it follows from the above that the CRYPTO-frame stream is not subject
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | snps,dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
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| H A D | dwc3.txt | 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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| /freebsd/share/man/man4/ |
| H A D | gve.4 | 1 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
87 Change the RX queue count to 4 for the gve0 interface:
93 Change the RX ring size to 512 for the gve0 interface:
97 .Bl -diag
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| H A D | bce.4 | 1 .\" Copyright (c) 2006-2014 QLogic Corporation
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
62 .Bl -item -offset indent -compact
72 10/100/1000Mbps operation in full-duplex mode
74 10/100Mbps operation in half-duplex mode
80 .Bl -tag -width ".Cm 10baseT/UTP"
92 .Cm full-duplex
94 .Cm half-duplex
102 .Cm full-duplex
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| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
69 interrupt vector per Tx/Rx queue pair, and CPU cacheline optimized
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| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | mvebu-uart.txt | 2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
15 compatible string for backward compatibility), it will only work
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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| /freebsd/sys/net/ |
| H A D | netmap.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2011-2014 Matteo Landi, Luigi Rizzo. All rights reserved.
48 * Some fields should be cache-aligned to reduce contention.
56 * --- Netmap data structures ---
68 +---->+---------------+
71 +----------------+ / | other fields |
75 | | / +---------------+
77 | txring_ofs[0] | (rel.to nifp)--' | flags, ptr |
78 | txring_ofs[1] | +---------------+
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| /freebsd/sys/net80211/ |
| H A D | ieee80211_ioctl.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
42 uint32_t ns_rx_data; /* rx data frames */
43 uint32_t ns_rx_mgmt; /* rx management frames */
44 uint32_t ns_rx_ctrl; /* rx control frames */
45 uint32_t ns_rx_ucast; /* rx unicast frames */
46 uint32_t ns_rx_mcast; /* rx multi/broadcast frames */
47 uint64_t ns_rx_bytes; /* rx data count (bytes) */
48 uint64_t ns_rx_beacons; /* rx beacon frames */
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | omap-mailbox.txt | 16 programmable through a set of interrupt configuration registers, and have a rx
18 is achieved through the appropriate programming of the rx and tx interrupt
25 routed to different processor sub-systems on DRA7xx as they are routed through
38 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
41 --------------------
42 - compatible: Should be one of the following,
43 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
44 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
45 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
47 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
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| H A D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
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| /freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
| H A D | rx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-9000 hardware */
26 * struct iwl_rx_phy_info - phy info
34 * @beacon_time_stamp: beacon at on-air rise
39 * @byte_count: frame's byte-count
46 * Before each Rx, the device sends this data. It contains PHY information
68 * TCP offload Rx assist info
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| /freebsd/sys/dev/ath/ath_hal/ |
| H A D | ah_desc.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
25 * in only after the tx descriptor process method finds a
30 * should be used only if non-zero.
55 int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
56 int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
77 * in only after the rx descriptor process method finds a
89 * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
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| /freebsd/sys/contrib/dev/athk/ath12k/ |
| H A D | rx_desc.h | 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
160 * is 2'b00, Rx OLE uses a REO destination indicati'n of {1'b1,
164 * 's not 2'b00, Rx OLE uses a REO destination indication of
169 * Indication to Rx OLE to enable REO destination routing based
186 * Field only valid when for the received frame type the corresponding
190 * Field only valid when for the received frame type the corresponding
202 * field in address search failure cache-only entry should
206 * If set, intra-BSS routing detection is enabled
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| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | fsl,cpm1-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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| H A D | fsl,qe-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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| /freebsd/sys/dev/rl/ |
| H A D | if_rlreg.h | 1 /*-
2 * Copyright (c) 1997, 1998-2003
16 * 4. Neither the name of the author nor the names of any co-contributors
37 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
42 /* 0006-0007 reserved */
62 #define RL_RXADDR 0x0030 /* RX ring start address */
63 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
64 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67 #define RL_CURRXBUF 0x003A /* current RX buffer address */
76 /* RTL8139/RTL8139C+ only */
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| /freebsd/sys/dev/ath/ath_hal/ar5416/ |
| H A D | ar5416desc.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
23 * Hardware-specific descriptor structures.
29 #define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 )
31 ((uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))
33 ((const uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))
53 struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */
72 struct ar5416_rx_desc rx; member
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