Lines Matching +full:rx +full:- +full:only
1 /*-
2 * Copyright (c) 1997, 1998-2003
16 * 4. Neither the name of the author nor the names of any co-contributors
37 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
42 /* 0006-0007 reserved */
62 #define RL_RXADDR 0x0030 /* RX ring start address */
63 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
64 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67 #define RL_CURRXBUF 0x003A /* current RX buffer address */
76 /* RTL8139/RTL8139C+ only */
91 /* 0059-005A reserved */
92 #define RL_MII 0x005A /* 8129 chip only */
99 /* Direct PHY access registers only available on 8139 */
141 #define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */
142 #define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */
153 #define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */
156 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
244 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */
245 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
246 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
247 #define RL_ISR_SWI 0x0100 /* C+ only */
249 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
271 * Media status register. (8139 only)
321 * Bits in RX status header (included with RX'ed packet
405 * MII register (8129 only)
437 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
487 * Config 2 register, 8139C+/8169/8169S/8110S only
502 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
503 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
504 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
528 * Gigabit PHY access register (8169 only)
535 * Gigabit media status (8169 only)
542 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
547 * The RealTek doesn't use a fragment-based descriptor mechanism.
548 * Instead, there are only four register sets, each of which represents
550 * packet buffer (32-bit aligned!) and we place the buffer addresses in
581 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
602 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
603 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
604 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
605 #define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
606 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
607 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
608 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
609 #define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
630 #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
631 (x)->rl_type == RL_8169)
634 * The 8139C+ and 8160 gigE chips support descriptor-based TX
635 * and RX. In fact, they even support TCP large send. Descriptors
637 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
641 * RX/TX descriptor definition. When large send mode is enabled, the
644 * the same for RX and TX descriptors
675 * Error bits are valid only on the last descriptor of a frame
681 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
687 * RX descriptor cmd/vlan definitions
704 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
713 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
714 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
735 * Statistics counter structure (8139C+ and 8169 only)
754 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
760 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
766 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
784 #define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
785 #define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
786 #define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
787 #define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
788 #define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
792 #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
809 #define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
814 (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
816 ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
818 ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
820 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
844 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
845 bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */
938 #define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
939 #define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
940 #define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
946 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
948 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
950 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
952 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
955 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
957 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
959 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
962 bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags)
1045 * D-Link vendor ID.
1050 * D-Link DFE-530TX+ device ID
1055 * D-Link DFE-520TX rev. C1 device ID
1060 * D-Link DFE-5280T device ID
1066 * D-Link DFE-690TXD device ID
1076 * Corega FEther CB-TXD device ID
1081 * Corega FEtherII CB-TXD device ID
1086 * Corega CG-LAPCIGT device ID
1101 * Linksys EG1032 rev 3 sub-device ID
1111 * Peppercon ROL-F device ID
1121 * Planex FNW-3603-TX device ID
1126 * Planex FNW-3800-TX device ID
1136 * LevelOne FPC-0106TX devide ID
1151 * Edimax EP-4103DL cardbus device ID