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/linux/arch/riscv/include/asm/
H A Dinsn-def.h32 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
33 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2
36 .macro insn_i, opcode, func3, rd, rs1, simm12
37 .insn i \opcode, \func3, \rd, \rs1, \simm12
40 .macro insn_s, opcode, func3, rs2, simm12, rs1
41 .insn s \opcode, \func3, \rs2, \simm12(\rs1)
48 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
53 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \
57 .macro insn_i, opcode, func3, rd, rs1, simm12
61 (.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) | \
[all …]
H A Dmodule.h76 * | imm[31:20] | rs1[19:15] | funct3 | rd[11:7] | opc[6:0] | in emit_plt_entry()
/linux/arch/sparc/kernel/
H A Dvisemul.c136 #define RS1(INSN) (((INSN) >> 14) & 0x1f) macro
140 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
143 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
296 unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val; in edge() local
299 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in edge()
300 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); in edge()
304 rs1 = rs1 & 0xffffffff; in edge()
311 left = edge8_tab[rs1 & 0x7].left; in edge()
316 left = edge8_tab_l[rs1 & 0x7].left; in edge()
322 left = edge16_tab[(rs1 >> 1) & 0x3].left; in edge()
[all …]
H A Dunaligned_32.c72 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
75 if(rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
139 unsigned int rs1 = (insn >> 14) & 0x1f; in compute_effective_address() local
144 maybe_flush_windows(rs1, 0, rd); in compute_effective_address()
145 return (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in compute_effective_address()
147 maybe_flush_windows(rs1, rs2, rd); in compute_effective_address()
148 return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address()
155 unsigned int rs1 = (insn >> 14) & 0x1f; in safe_compute_effective_address() local
160 maybe_flush_windows(rs1, 0, rd); in safe_compute_effective_address()
161 return (safe_fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in safe_compute_effective_address()
[all …]
H A Dunaligned_64.c104 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
107 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
173 unsigned int rs1 = (insn >> 14) & 0x1f; in compute_effective_address() local
178 maybe_flush_windows(rs1, 0, rd, from_kernel); in compute_effective_address()
179 addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in compute_effective_address()
181 maybe_flush_windows(rs1, rs2, rd, from_kernel); in compute_effective_address()
182 addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address()
/linux/arch/riscv/kernel/probes/
H A Dsimulate-insn.c65 * offset[11:0] | rs1 | 010 | rd | opcode in simulate_jalr()
144 * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode | in simulate_branch()
146 * imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 BEQ in simulate_branch()
147 * imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 BNE in simulate_branch()
148 * imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 BLT in simulate_branch()
149 * imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 BGE in simulate_branch()
150 * imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 BLTU in simulate_branch()
151 * imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 BGEU in simulate_branch()
221 * | funct4 | rs1 | rs2 | op | in simulate_c_jr_jalr()
227 u32 rs1 = (opcode >> 7) & 0x1f; in simulate_c_jr_jalr() local
[all …]
/linux/arch/riscv/errata/thead/
H A Derrata.c47 * th.dcache.ipa rs1 (invalidate, physical address)
49 * 0000001 01010 rs1 000 00000 0001011
50 * th.dcache.iva rs1 (invalidate, virtual address)
51 * 0000001 00110 rs1 000 00000 0001011
53 * th.dcache.cpa rs1 (clean, physical address)
55 * 0000001 01001 rs1 000 00000 0001011
56 * th.dcache.cva rs1 (clean, virtual address)
57 * 0000001 00101 rs1 000 00000 0001011
59 * th.dcache.cipa rs1 (clean then invalidate, physical address)
61 * 0000001 01011 rs1 000 00000 0001011
[all …]
/linux/arch/sparc/net/
H A Dbpf_jit_comp_32.c26 #define RS1(X) ((X) << 14) macro
71 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
113 *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \
118 *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \
123 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
140 *prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A); \
161 _insn |= RS1(r_A) | RD(r_A); \
175 *prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST); \
184 *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
190 *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \
[all …]
H A Dbpf_jit_comp_64.c55 #define RS1(X) ((X) << 14) macro
139 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
263 emit(OR | RS1(G0) | RS2(from) | RD(to), ctx); in emit_reg_move()
284 emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx); in emit_set_const_sext()
290 emit(opcode | RS1(dst) | RS2(src) | RD(dst), ctx); in emit_alu()
295 emit(opcode | RS1(a) | RS2(b) | RD(c), ctx); in emit_alu3()
304 insn |= RS1(dst) | RD(dst); in emit_alu_K()
323 insn |= RS1(src) | RD(dst); in emit_alu3_K()
340 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); in emit_loadimm32()
350 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); in emit_loadimm()
[all …]
/linux/arch/arm64/kernel/
H A Dsleep.S15 * @rs1: register containing affinity level 1 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
32 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
44 lsr \mask ,\mask, \rs1
45 orr \dst, \dst, \mask // dst|=(aff1>>rs1)
/linux/arch/arm/kernel/
H A Dsleep.S16 * @rs1: register containing affinity level 1 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
31 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
33 * Input registers: rs0, rs1, rs2, mpidr, mask
38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
44 ARM( orr \dst, \dst, \mask, lsr \rs1 ) @ dst|=(aff1>>rs1)
45 THUMB( lsr \mask, \mask, \rs1 )
/linux/arch/riscv/net/
H A Dbpf_jit_comp32.c571 const s8 *rs1 = bpf_get_reg64(src1, tmp1, ctx); in emit_branch_r64() local
587 emit(rv_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
588 emit(rv_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
591 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
592 emit(rv_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
593 emit(rv_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
596 emit(rv_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
597 emit(rv_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
598 emit(rv_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
601 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
[all …]
/linux/arch/parisc/net/
H A Dbpf_jit_comp32.c706 const s8 *rs1 = bpf_get_reg64(src1, tmp1, ctx); in emit_branch_r64() local
722 emit(hppa_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
723 emit(hppa_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
726 emit(hppa_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
727 emit(hppa_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
728 emit(hppa_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
731 emit(hppa_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
732 emit(hppa_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
733 emit(hppa_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
736 emit(hppa_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
[all …]
/linux/arch/arm/include/debug/
H A Dvexpress.S28 @ - all other (RS1 complaint) tiles use UART mapped
40 @ RS1 memory map
/linux/arch/sparc/math-emu/
H A Dmath_32.c279 /* r is rd, b is rs2 and a is rs1. The *u arg tells in do_one_mathemu()
284 argp rs1 = NULL, rs2 = NULL, rd = NULL; in do_one_mathemu() local
355 switch (type & 0x3) { /* is rs1 single, double or quad? */ in do_one_mathemu()
369 rs1 = (argp)&fregs[freg]; in do_one_mathemu()
371 case 7: FP_UNPACK_QP (QA, rs1); break; in do_one_mathemu()
372 case 6: FP_UNPACK_DP (DA, rs1); break; in do_one_mathemu()
373 case 5: FP_UNPACK_SP (SA, rs1); break; in do_one_mathemu()
H A Dmath_64.c173 /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells in do_mathemu()
359 argp rs1 = NULL, rs2 = NULL, rd = NULL; in do_mathemu() local
380 case 1: rs1 = (argp)&f->regs[freg]; in do_mathemu()
383 rs1 = (argp)&zero; in do_mathemu()
387 case 7: FP_UNPACK_QP (QA, rs1); break; in do_mathemu()
388 case 6: FP_UNPACK_DP (DA, rs1); break; in do_mathemu()
389 case 5: FP_UNPACK_SP (SA, rs1); break; in do_mathemu()
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m.dtsi14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
H A Dvexpress-v2p-ca5s.dts12 #include "vexpress-v2m-rs1.dtsi"
H A Dvexpress-v2p-ca15-tc1.dts12 #include "vexpress-v2m-rs1.dtsi"
/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts80 arm,v2m-memory-map = "rs1";
/linux/tools/testing/selftests/riscv/vector/
H A Dv_exec_initval_nolibc.c22 // 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli in main()
/linux/arch/arm64/boot/dts/arm/
H A Dvexpress-v2f-1xv7-ca53x2.dts16 #include "arm/arm/vexpress-v2m-rs1.dtsi"
/linux/drivers/edac/
H A Dpnd2_edac.h224 u32 rs1 : 5; member
/linux/include/linux/rtc/
H A Dds1685.h154 #define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */
311 /* E32K RS3 RS2 RS1 RS0 */
/linux/arch/arc/net/
H A Dbpf_jit_arcv2.c1138 static u8 arc_or_r(u8 *buf, u8 rd, u8 rs1, u8 rs2) in arc_or_r() argument
1140 const u32 insn = OPC_OR | OP_A(rd) | OP_B(rs1) | OP_C(rs2); in arc_or_r()
1196 static u8 arc_asl_r(u8 *buf, u8 rd, u8 rs1, u8 rs2) in arc_asl_r() argument
1198 const u32 insn = OPC_ASL | OP_A(rd) | OP_B(rs1) | OP_C(rs2); in arc_asl_r()
1214 static u8 arc_asr_r(u8 *buf, u8 rd, u8 rs1, u8 rs2) in arc_asr_r() argument
1216 const u32 insn = OPC_ASR | OP_A(rd) | OP_B(rs1) | OP_C(rs2); in arc_asr_r()
1232 static u8 arc_lsr_r(u8 *buf, u8 rd, u8 rs1, u8 rs2) in arc_lsr_r() argument
1234 const u32 insn = OPC_LSR | OP_A(rd) | OP_B(rs1) | OP_C(rs2); in arc_lsr_r()

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