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/freebsd/contrib/file/magic/Magdir/
H A Dacorn7 # RISC OS Chunk File Format
8 # From RISC OS Programmer's Reference Manual, Appendix D
10 0 lelong 0xc3cbc6c5 RISC OS Chunk data
14 # RISC OS AIF, contains "SWI OS_Exit" at offset 16.
15 16 lelong 0xef000011 RISC OS AIF executable
17 # RISC OS Draw files
18 # From RISC OS Programmer's Reference Manual, Appendix E
19 0 string Draw RISC OS Draw file data
21 # RISC OS new format font files
22 # From RISC OS Programmer's Reference Manual, Appendix E
[all …]
H A Delf42 0 name elf-pa-risc
113 >18 leshort 15 PA-RISC,
116 >>>36 use elf-pa-risc
119 >>>48 use elf-pa-risc
152 >18 leshort 45 Argonaut RISC Core, Argonaut Technologies Inc.,
216 >18 leshort 109 Arca RISC,
226 >18 leshort 119 Freescale RISC core,
231 >18 leshort 135 Sunplus S+core7 RISC,
247 >18 leshort 167 Andes embedded RISC,
251 >18 leshort 171 M2000 Reconfigurable RISC,
[all …]
H A Dcoff35 # executable (RISC System/6000 V3.1) or obj module (./ibm6000 v 1.15), not PE/COFF
36 >0 uleshort 0x01df RISC System/6000
44 >0 uleshort 0x0290 PA-RISC
60 >0 uleshort 0x5032 RISC-V 32-bit
61 >0 uleshort 0x5064 RISC-V 64-bit
62 >0 uleshort 0x5128 RISC-V 128-bit
82 # flag bits (0x0800,0x0400,0x0200) now seems to be used in RISC System/6000 V3.1
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Driscv,timer.yaml7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
/freebsd/share/i18n/csmapper/MISC/
H A DRISCOS-LATIN1%UCS.src14 # The charset used on RISC OS ('Acorn RISC OS'). The same as Latin-1,
20 # Now the RISC OS specific characters. This is from RISC OS 3.11. In
21 # earlier versions of RISC OS, some of these were used for drawing
27 # in Homerton, one of the outline fonts that comes with RISC OS. The
29 # supplied by EFF, a third-party supplier of RISC OS outline fonts.
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,imsics.yaml7 title: RISC-V Incoming MSI Controller (IMSIC)
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
24 The device tree of a RISC-V platform will have one IMSIC device tree node
28 The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
29 follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
32 RISC-V platform. The MSI target address of a IMSIC interrupt file at given
75 to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
18 All RISC-V systems that conform to the supervisor ISA specification are
29 RISC-V supervisor ISA manual, with only the following three interrupts being
H A Driscv,cpu-intc.yaml7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
25 All RISC-V systems that conform to the supervisor ISA specification are
50 The interrupt sources are defined by the RISC-V supervisor ISA manual,
H A Driscv,aplic.yaml7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
15 in a RISC-V platform. The RISC-V AIA specification can be found at
18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all
46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
47 node, which has a CPU node (i.e. RISC-V HART) as parent.
H A Dsifive,plic-1.0.0.yaml11 SiFive SoCs and other RISC-V SoCs include an implementation of the
13 the RISC-V Privileged Architecture specification. The PLIC connects all
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml7 title: RISC-V ISA extensions
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
134 added by other RISC-V extensions in H/S/VS/U/VU modes and as
216 in version 1.0 of RISC-V Cryptography Extensions Volume I
222 in version 1.0 of RISC-V Cryptography Extensions Volume I
228 in version 1.0 of RISC-V Cryptography Extensions Volume I
296 in version 1.0 of RISC-V Cryptography Extensions Volume I
[all …]
H A Dcpus.yaml7 title: RISC-V CPUs
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
62 Identifies that the hart uses the RISC-V instruction set
68 this hart. These values originate from the RISC-V Privileged
98 # RISC-V has multiple properties for cache op block sizes as the sizes
101 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_riscvcap.pod5 OPENSSL_riscvcap - the RISC-V processor capabilities vector
13 libcrypto supports RISC-V instruction set extensions. These
16 returned by the RISC-V Hardware Probing syscall (hwprobe) are stored
23 The environment variable is similar to the RISC-V ISA string defined in the
24 RISC-V Instruction Set Manual. It is case insensitive. Though due to the limit
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVISAInfo.h1 //===-- RISCVISAInfo.h - RISC-V ISA Information -----------------*- C++ -*-===//
29 /// Parse RISC-V ISA info from arch string.
38 /// Parse RISC-V ISA info from an arch string that is already in normalized
44 /// Parse RISC-V ISA info from feature vector.
52 /// Convert RISC-V ISA info to a feature vector.
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCV.td1 //===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===//
12 // RISC-V subtarget features and instruction predicates.
18 // RISC-V profiles supported.
40 // RISC-V macro fusions.
46 // RISC-V Scheduling Models
58 // RISC-V processors supported.
64 // Define the RISC-V target.
H A DRISCVISelDAGToDAG.h1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
9 // This file defines an instruction selector for the RISC-V target.
21 // RISC-V specific code to select RISC-V machine instructions for
166 // Return the RISC-V condition code that matches the given DAG integer
167 // condition code. The CondCode must be one of those supported by the RISC-V
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.h1 //===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===//
9 // This file provides RISC-V specific target descriptions.
55 // Defines symbolic names for RISC-V registers.
59 // Defines symbolic names for RISC-V instructions.
H A DRISCVTargetStreamer.cpp1 //===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
9 // This file provides RISC-V specific target streamer methods.
25 // like RISC-V atomics or X3 usage.
28 cl::desc("Enable emitting RISC-V ELF attributes for ABI features"),
/freebsd/crypto/openssl/providers/implementations/ciphers/
H A Dcipher_aes_gcm_hw_rv64i.inc11 * RISC-V 64 support for AES GCM.
16 * RISC-V 64 ZKND and ZKNE support for AES GCM.
38 * RISC-V RV64 ZVKNED support for AES GCM.
71 * RISC-V RV64 ZVKB, ZVKG and ZVKNED support for AES GCM.
/freebsd/contrib/llvm-project/clang/include/clang/Sema/
H A DSemaRISCV.h1 //===----- SemaRISCV.h ---- RISC-V target-specific routines ---*- C++ -*---===//
9 /// This file declares semantic analysis functions specific to RISC-V.
44 /// Indicate RISC-V vector builtin functions enabled or not.
47 /// Indicate RISC-V SiFive vector builtin functions enabled or not.
H A DRISCVIntrinsicManager.h1 //===- RISCVIntrinsicManager.h - RISC-V Intrinsic Handler -------*- C++ -*-===//
9 // This file defines the RISCVIntrinsicManager, which handles RISC-V vector
33 // Create RISC-V intrinsic and insert into symbol table and return true if
/freebsd/sys/crypto/des/
H A Ddes_ecb.c66 const char *ptr,*unroll,*risc,*size; in des_options() local
75 risc="risc1"; in des_options()
78 risc="risc2"; in des_options()
81 risc="cisc"; in des_options()
92 sprintf(buf,"des(%s,%s,%s,%s)",ptr,risc,unroll,size); in des_options()
/freebsd/contrib/xz/src/liblzma/api/lzma/
H A Dbcj.h56 * \brief Filter for RISC-V binaries
137 * \brief Raw RISC-V BCJ encoder
142 * executable being filtered. For the RISC-V
148 * `size`. With the RISC-V filter, the return value is always
157 * \brief Raw RISC-V BCJ decoder
/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_riscvcap.364 OPENSSL_riscvcap \- the RISC\-V processor capabilities vector
72 libcrypto supports RISC-V instruction set extensions. These
75 returned by the RISC-V Hardware Probing syscall (hwprobe) are stored
82 The environment variable is similar to the RISC-V ISA string defined in the
83 RISC-V Instruction Set Manual. It is case insensitive. Though due to the limit
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/TargetInfo/
H A DRISCVTargetInfo.cpp1 //===-- RISCVTargetInfo.cpp - RISC-V Target Implementation ----------------===//
25 getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV"); in LLVMInitializeRISCVTargetInfo()
27 getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV"); in LLVMInitializeRISCVTargetInfo()

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