106c3fb27SDimitry Andric//===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 100b57cec5SDimitry Andric 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric// RISC-V subtarget features and instruction predicates. 130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 15bdd1243dSDimitry Andricinclude "RISCVFeatures.td" 1604eeddc0SDimitry Andric 170b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18*0fca6ea1SDimitry Andric// RISC-V profiles supported. 19*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 20*0fca6ea1SDimitry Andric 21*0fca6ea1SDimitry Andricinclude "RISCVProfiles.td" 22*0fca6ea1SDimitry Andric 23*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 240b57cec5SDimitry Andric// Named operands for CSR instructions. 250b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 260b57cec5SDimitry Andric 270b57cec5SDimitry Andricinclude "RISCVSystemOperands.td" 280b57cec5SDimitry Andric 290b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 300b57cec5SDimitry Andric// Registers, calling conventions, instruction descriptions. 310b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 320b57cec5SDimitry Andric 330b57cec5SDimitry Andricinclude "RISCVRegisterInfo.td" 34*0fca6ea1SDimitry Andricinclude "RISCVSchedule.td" 350b57cec5SDimitry Andricinclude "RISCVCallingConv.td" 360b57cec5SDimitry Andricinclude "RISCVInstrInfo.td" 37bdd1243dSDimitry Andricinclude "GISel/RISCVRegisterBanks.td" 38bdd1243dSDimitry Andric 39bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 40b3edf446SDimitry Andric// RISC-V macro fusions. 41b3edf446SDimitry Andric//===----------------------------------------------------------------------===// 42b3edf446SDimitry Andric 43b3edf446SDimitry Andricinclude "RISCVMacroFusion.td" 44b3edf446SDimitry Andric 45b3edf446SDimitry Andric//===----------------------------------------------------------------------===// 46bdd1243dSDimitry Andric// RISC-V Scheduling Models 47bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 48bdd1243dSDimitry Andric 49e8d8bef9SDimitry Andricinclude "RISCVSchedRocket.td" 50e8d8bef9SDimitry Andricinclude "RISCVSchedSiFive7.td" 517a6dacacSDimitry Andricinclude "RISCVSchedSiFiveP400.td" 52*0fca6ea1SDimitry Andricinclude "RISCVSchedSiFiveP600.td" 53bdd1243dSDimitry Andricinclude "RISCVSchedSyntacoreSCR1.td" 54*0fca6ea1SDimitry Andricinclude "RISCVSchedSyntacoreSCR3.td" 55*0fca6ea1SDimitry Andricinclude "RISCVSchedXiangShanNanHu.td" 560b57cec5SDimitry Andric 570b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 580b57cec5SDimitry Andric// RISC-V processors supported. 590b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 600b57cec5SDimitry Andric 61bdd1243dSDimitry Andricinclude "RISCVProcessors.td" 6213138422SDimitry Andric 630b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 640b57cec5SDimitry Andric// Define the RISC-V target. 650b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 660b57cec5SDimitry Andric 670b57cec5SDimitry Andricdef RISCVInstrInfo : InstrInfo { 680b57cec5SDimitry Andric let guessInstructionProperties = 0; 690b57cec5SDimitry Andric} 700b57cec5SDimitry Andric 710b57cec5SDimitry Andricdef RISCVAsmParser : AsmParser { 720b57cec5SDimitry Andric let ShouldEmitMatchRegisterAltName = 1; 730b57cec5SDimitry Andric let AllowDuplicateRegisterNames = 1; 740b57cec5SDimitry Andric} 750b57cec5SDimitry Andric 760b57cec5SDimitry Andricdef RISCVAsmWriter : AsmWriter { 770b57cec5SDimitry Andric int PassSubtarget = 1; 780b57cec5SDimitry Andric} 790b57cec5SDimitry Andric 800b57cec5SDimitry Andricdef RISCV : Target { 810b57cec5SDimitry Andric let InstructionSet = RISCVInstrInfo; 820b57cec5SDimitry Andric let AssemblyParsers = [RISCVAsmParser]; 830b57cec5SDimitry Andric let AssemblyWriters = [RISCVAsmWriter]; 840b57cec5SDimitry Andric let AllowRegisterRenaming = 1; 850b57cec5SDimitry Andric} 86