| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | riscv,timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
[all …]
|
| H A D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | riscv,imsics.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
[all …]
|
| H A D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
[all …]
|
| H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
[all …]
|
| H A D | riscv,aplic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all
[all …]
|
| H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
[all …]
|
| /freebsd/share/i18n/csmapper/MISC/ |
| H A D | RISCOS-LATIN1%UCS.src | 1 # $NetBSD: RISCOS-LATIN1%UCS.src,v 1.1 2007/04/01 18:52:29 tnozaki Exp $
4 NAME "RISCOS-LATIN1/UCS"
5 SRC_ZONE 0x00-0xFF
12 # Id: RISCOS.TXT,v 1.1 2003/05/19 20:26:32 mleisher Exp
14 # The charset used on RISC OS ('Acorn RISC OS'). The same as Latin-1,
17 # -- Ed Avis, <ed@membled.com>, 2001-03-08
19 # First everything from Latin-1 outside 0x80 -| 0xA0.
20 # Now the RISC OS specific characters. This is from RISC OS 3.11. In
21 # earlier versions of RISC OS, some of these were used for drawing
27 # in Homerton, one of the outline fonts that comes with RISC OS. The
[all …]
|
| /freebsd/contrib/file/magic/Magdir/ |
| H A D | acorn | 2 #------------------------------------------------------------------------------
3 # $File: acorn,v 1.9 2024/08/30 17:29:28 christos Exp $
7 # RISC OS Chunk File Format
8 # From RISC OS Programmer's Reference Manual, Appendix D
10 0 lelong 0xc3cbc6c5 RISC OS Chunk data
14 # RISC OS AIF, contains "SWI OS_Exit" at offset 16.
15 16 lelong 0xef000011 RISC OS AIF executable
17 # RISC OS Draw files
18 # From RISC OS Programmer's Reference Manual, Appendix E
19 0 string Draw RISC OS Draw file data
[all …]
|
| H A D | coff | 2 #------------------------------------------------------------------------------
3 # $File: coff,v 1.15 2024/11/10 18:54:33 christos Exp $
12 # https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#coff-file-header-object-and-image
16 0 name display-coff-processor
20 >0 uleshort 0x0160 MIPS R3000 (big-endian)
25 >0 uleshort 0x0184 Alpha 32-bit
35 # executable (RISC System/6000 V3.1) or obj module (./ibm6000 v 1.15), not PE/COFF
36 >0 uleshort 0x01df RISC System/6000
37 >0 uleshort 0x01f0 PowerPC 32-bit (little-endian)
38 >0 uleshort 0x01f1 PowerPC 32-bit with FPU (little-endian)
[all …]
|
| H A D | elf | 2 #------------------------------------------------------------------------------
3 # $File: elf,v 1.91 2024/11/09 23:52:23 christos Exp $
15 # Modified by (2): Peter Tobias <tobias@server.et-inf.fho-emden.de> (core support)
20 0 name elf-mips
21 >0 lelong&0xf0000000 0x00000000 MIPS-I
22 >0 lelong&0xf0000000 0x10000000 MIPS-II
23 >0 lelong&0xf0000000 0x20000000 MIPS-III
24 >0 lelong&0xf0000000 0x30000000 MIPS-IV
25 >0 lelong&0xf0000000 0x40000000 MIPS-V
33 0 name elf-sparc
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/ |
| H A D | RISCVISAInfo.h | 1 //===-- RISCVISAInfo.h - RISC-V ISA Information -----------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
29 /// Parse RISC-V ISA info from arch string.
38 /// Parse RISC-V ISA info from an arch string that is already in normalized
44 /// Parse RISC-V ISA info from feature vector.
52 /// Convert RISC-V ISA info to a feature vector.
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCV.td | 1 //===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
12 // RISC-V subtarget features and instruction predicates.
13 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // RISC-V profiles supported.
19 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
[all …]
|
| H A D | RISCVISelDAGToDAG.h | 1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines an instruction selector for the RISC-V target.
11 //===----------------------------------------------------------------------===//
21 // RISC-V specific code to select RISC-V machine instructions for
72 if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) { in SelectAddrRegZextRegScale()
89 return selectShiftMask(N, Subtarget->getXLen(), ShAmt); in selectShiftMaskXLen()
166 // Return the RISC-V condition code that matches the given DAG integer
167 // condition code. The CondCode must be one of those supported by the RISC-V
|
| H A D | RISCVCallingConv.td | 1 //===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for the RISC-V architecture.
11 //===----------------------------------------------------------------------===//
13 // The RISC-V calling convention is handled with custom code in
29 defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31),
49 // Same as CSR_Interrupt, but including all 32-bit FP registers.
53 // Same as CSR_Interrupt, but including all 64-bit FP registers.
57 // Same as CSR_Interrupt, but excluding X16-X31.
[all …]
|
| H A D | RISCVFrameLowering.h | 1 //===-- RISCVFrameLowering.h - Define frame lowering for RISC-V -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This class implements RISC-V specific bits of TargetFrameLowering class.
11 //===----------------------------------------------------------------------===//
78 // We don't support putting RISC-V Vector objects into the pre-allocated in isStackIdSafeForLocalArea()
|
| H A D | RISCVRedundantCopyElimination.cpp | 1 //=- RISCVRedundantCopyElimination.cpp - Remove useless copy for RISC-V -----=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
22 // do on RISC-V since branches can't have immediates.
24 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "riscv-copyelim"
59 return "RISC-V Redundant Copy Elimination"; in getPassName()
70 INITIALIZE_PASS(RISCVRedundantCopyElimination, "riscv-copyelim",
71 "RISC-V Redundant Copy Elimination", false, false)
97 if (PredMBB->succ_size() != 2) in optimizeBlock()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMCTargetDesc.h | 1 //===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file provides RISC-V specific target descriptions.
11 //===----------------------------------------------------------------------===//
55 // Defines symbolic names for RISC-V registers.
59 // Defines symbolic names for RISC-V instructions.
|
| H A D | RISCVTargetStreamer.cpp | 1 //===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file provides RISC-V specific target streamer methods.
11 //===----------------------------------------------------------------------===//
25 // like RISC-V atomics or X3 usage.
27 "riscv-abi-attributes",
28 cl::desc("Enable emitting RISC-V ELF attributes for ABI features"),
84 emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString()); in emitTargetAttributes()
145 OS << "-"; in emitDirectiveOptionArch()
|
| /freebsd/contrib/llvm-project/clang/include/clang/Sema/ |
| H A D | SemaRISCV.h | 1 //===----- SemaRISCV.h ---- RISC-V target-specific routines ---*- C++ -*---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file declares semantic analysis functions specific to RISC-V.
11 //===----------------------------------------------------------------------===//
44 /// Indicate RISC-V vector builtin functions enabled or not.
47 /// Indicate RISC-V SiFive vector builtin functions enabled or not.
|
| H A D | RISCVIntrinsicManager.h | 1 //===- RISCVIntrinsicManager.h - RISC-V Intrinsic Handler -------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the RISCVIntrinsicManager, which handles RISC-V vector
12 //===----------------------------------------------------------------------===//
33 // Create RISC-V intrinsic and insert into symbol table and return true if
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/TargetInfo/ |
| H A D | RISCVTargetInfo.cpp | 1 //===-- RISCVTargetInfo.cpp - RISC-V Target Implementation ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
25 getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV"); in LLVMInitializeRISCVTargetInfo()
27 getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV"); in LLVMInitializeRISCVTargetInfo()
|
| /freebsd/sys/crypto/des/ |
| H A D | des_ecb.c | 1 /* $KAME: des_ecb.c,v 1.6 2001/09/10 04:03:58 itojun Exp $ */
5 /* Copyright (C) 1995-1998 Eric Young (eay@mincom.oz.au)
12 * FREE FOR COMMERCIAL AND NON-COMMERCIAL USE
56 /* char *libdes_version="libdes v 3.24 - 20-Apr-1996 - eay"; */ /* wrong */
57 /* char *DES_version="DES part of SSLeay 0.6.4 30-Aug-1996"; */
66 const char *ptr,*unroll,*risc,*size; in des_options() local
75 risc="risc1"; in des_options()
78 risc="risc2"; in des_options()
81 risc="cisc"; in des_options()
92 sprintf(buf,"des(%s,%s,%s,%s)",ptr,risc,unroll,size); in des_options()
|
| /freebsd/sys/riscv/riscv/ |
| H A D | timer.c | 1 /*-
2 * Copyright (c) 2015-2024 Ruslan Bukin <br@bsdpad.com>
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
36 * RISC-V Timer
72 .tc_name = "RISC-V Timecounter",
109 vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME; in riscv_timer_tc_fill_vdso_timehands()
110 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); in riscv_timer_tc_fill_vdso_timehands()
120 counts = ((uint32_t)et->et_frequency * first) >> 32; in riscv_timer_et_start()
147 csr_write(stimecmp, -1UL); in riscv_timer_intr()
151 if (sc->et.et_active) in riscv_timer_intr()
[all …]
|