106c3fb27SDimitry Andric//===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 906c3fb27SDimitry Andric// This describes the calling conventions for the RISC-V architecture. 100b57cec5SDimitry Andric// 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric// The RISC-V calling convention is handled with custom code in 140b57cec5SDimitry Andric// RISCVISelLowering.cpp (CC_RISCV). 150b57cec5SDimitry Andric 167a6dacacSDimitry Andricdef CSR_ILP32E_LP64E : CalleeSavedRegs<(add X1, X8, X9)>; 177a6dacacSDimitry Andric 180b57cec5SDimitry Andricdef CSR_ILP32_LP64 197a6dacacSDimitry Andric : CalleeSavedRegs<(add CSR_ILP32E_LP64E, (sequence "X%u", 18, 27))>; 200b57cec5SDimitry Andric 210b57cec5SDimitry Andricdef CSR_ILP32F_LP64F 220b57cec5SDimitry Andric : CalleeSavedRegs<(add CSR_ILP32_LP64, 238bcb0991SDimitry Andric F8_F, F9_F, (sequence "F%u_F", 18, 27))>; 240b57cec5SDimitry Andric 250b57cec5SDimitry Andricdef CSR_ILP32D_LP64D 260b57cec5SDimitry Andric : CalleeSavedRegs<(add CSR_ILP32_LP64, 278bcb0991SDimitry Andric F8_D, F9_D, (sequence "F%u_D", 18, 27))>; 280b57cec5SDimitry Andric 29*0fca6ea1SDimitry Andricdefvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31), 30*0fca6ea1SDimitry Andric V2M2, V4M2, V6M2, V24M2, V26M2, V28M2, V30M2, 31*0fca6ea1SDimitry Andric V4M4, V24M4, V28M4, V24M8); 32*0fca6ea1SDimitry Andric 33*0fca6ea1SDimitry Andricdef CSR_ILP32_LP64_V 34*0fca6ea1SDimitry Andric : CalleeSavedRegs<(add CSR_ILP32_LP64, CSR_V)>; 35*0fca6ea1SDimitry Andric 36*0fca6ea1SDimitry Andricdef CSR_ILP32F_LP64F_V 37*0fca6ea1SDimitry Andric : CalleeSavedRegs<(add CSR_ILP32F_LP64F, CSR_V)>; 38*0fca6ea1SDimitry Andric 39*0fca6ea1SDimitry Andricdef CSR_ILP32D_LP64D_V 40*0fca6ea1SDimitry Andric : CalleeSavedRegs<(add CSR_ILP32D_LP64D, CSR_V)>; 41*0fca6ea1SDimitry Andric 420b57cec5SDimitry Andric// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask() 430b57cec5SDimitry Andricdef CSR_NoRegs : CalleeSavedRegs<(add)>; 440b57cec5SDimitry Andric 450b57cec5SDimitry Andric// Interrupt handler needs to save/restore all registers that are used, 460b57cec5SDimitry Andric// both Caller and Callee saved registers. 47647cbc5dSDimitry Andricdef CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 31))>; 480b57cec5SDimitry Andric 490b57cec5SDimitry Andric// Same as CSR_Interrupt, but including all 32-bit FP registers. 5006c3fb27SDimitry Andricdef CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, 5106c3fb27SDimitry Andric (sequence "F%u_F", 0, 31))>; 520b57cec5SDimitry Andric 530b57cec5SDimitry Andric// Same as CSR_Interrupt, but including all 64-bit FP registers. 5406c3fb27SDimitry Andricdef CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, 5506c3fb27SDimitry Andric (sequence "F%u_D", 0, 31))>; 567a6dacacSDimitry Andric 577a6dacacSDimitry Andric// Same as CSR_Interrupt, but excluding X16-X31. 587a6dacacSDimitry Andricdef CSR_Interrupt_RVE : CalleeSavedRegs<(sub CSR_Interrupt, 597a6dacacSDimitry Andric (sequence "X%u", 16, 31))>; 607a6dacacSDimitry Andric 617a6dacacSDimitry Andric// Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31. 627a6dacacSDimitry Andricdef CSR_XLEN_F32_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_Interrupt, 637a6dacacSDimitry Andric (sequence "X%u", 16, 31))>; 647a6dacacSDimitry Andric 657a6dacacSDimitry Andric// Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31. 667a6dacacSDimitry Andricdef CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt, 677a6dacacSDimitry Andric (sequence "X%u", 16, 31))>; 68