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/linux/drivers/clk/qcom/
H A Dclk-rcg.c15 #include "clk-rcg.h"
39 struct clk_rcg *rcg = to_clk_rcg(hw); in clk_rcg_get_parent() local
44 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent()
47 ns = ns_to_src(&rcg->s, ns); in clk_rcg_get_parent()
49 if (ns == rcg->s.parent_map[i].cfg) in clk_rcg_get_parent()
58 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) in reg_to_bank() argument
60 bank &= BIT(rcg->mux_sel_bit); in reg_to_bank()
66 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); in clk_dyn_rcg_get_parent() local
73 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_get_parent()
76 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_get_parent()
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H A Dclk-rcg2.c23 #include "clk-rcg.h"
49 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) argument
50 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) argument
51 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) argument
52 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) argument
69 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_is_enabled() local
73 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in clk_rcg2_is_enabled()
82 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_get_parent() local
90 if (cfg == rcg->parent_map[i].cfg) in __clk_rcg2_get_parent()
100 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_get_parent() local
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H A Dclk-regmap-mux-div.c54 pr_err("%s: RCG did not update its configuration", name); in mux_div_set_src_div()
68 pr_err("%s: RCG configuration is pending\n", name); in mux_div_get_src_div()
H A Dapss-ipq6018.c22 #include "clk-rcg.h"
H A Dtcsrcc-sm8550.c19 #include "clk-rcg.h"
H A Dgpucc-sc7180.c16 #include "clk-rcg.h"
H A Dapss-ipq5424.c22 #include "clk-rcg.h"
H A Dtcsrcc-glymur.c18 #include "clk-rcg.h"
H A Dvideocc-sc7280.c16 #include "clk-rcg.h"
H A Dgpucc-sm8250.c18 #include "clk-rcg.h"
H A Dgpucc-sm8150.c18 #include "clk-rcg.h"
H A Dgpucc-qcm2290.c19 #include "clk-rcg.h"
H A Dvideocc-sm8250.c16 #include "clk-rcg.h"
H A Dgpucc-sm6125.c17 #include "clk-rcg.h"
H A Dvideocc-milos.c17 #include "clk-rcg.h"
H A Dgpucc-sm6375.c18 #include "clk-rcg.h"
H A Dlpasscorecc-sc7180.c18 #include "clk-rcg.h"
H A DMakefile8 clk-qcom-y += clk-rcg.o
H A Dgpucc-sm6115.c17 #include "clk-rcg.h"
H A Dlcc-ipq806x.c20 #include "clk-rcg.h"
H A Dcommon.c19 #include "clk-rcg.h"
H A Dgpucc-sm6350.c18 #include "clk-rcg.h"
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq5424-apss-clk.yaml13 The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
14 The RCG and PLL have a separate register space from the GCC.
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c325 /* TBD add symclk_be in rcg control bits */ in dccg35_set_symclk_be_rcg()
953 /* Make sure FE is not already in RCG */ in dccg35_disable_symclk_be_new()
959 /* Safe to RCG SYMCLK*/ in dccg35_disable_symclk_be_new()
1000 /* Make sure FE is not already in RCG */ in dccg35_disable_symclk32_le_new()
1002 /* Disable and SE connected to this LE before RCG */ in dccg35_disable_symclk32_le_new()
1007 /* Safe to RCG SYM32_LE*/ in dccg35_disable_symclk32_le_new()
1754 /* Any RCG should be done when driver enter low power mode*/ in dccg35_init_cb()
2258 /* Redundant RCG already done in disable_physymclk in dccg35_set_physymclk_root_clock_gating_cb()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c1376 print_pg_status(dc, __func__, ": after rcg and power up"); in dcn35_prepare_bandwidth()
1385 print_pg_status(dc, __func__, ": before rcg and power up"); in dcn35_optimize_bandwidth()
1399 print_pg_status(dc, __func__, ": after rcg and power up"); in dcn35_optimize_bandwidth()
1581 * Re-use hwss func and existing PG&RCG flags to decide powerup sequence.

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