Lines Matching full:rcg
23 #include "clk-rcg.h"
49 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) argument
50 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) argument
51 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) argument
52 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) argument
69 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_is_enabled() local
73 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in clk_rcg2_is_enabled()
82 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_get_parent() local
90 if (cfg == rcg->parent_map[i].cfg) in __clk_rcg2_get_parent()
100 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_get_parent() local
104 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_get_parent()
114 static int update_config(struct clk_rcg2 *rcg) in update_config() argument
118 struct clk_hw *hw = &rcg->clkr.hw; in update_config()
121 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in update_config()
128 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in update_config()
136 WARN(1, "%s: rcg didn't update its configuration.", name); in update_config()
142 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_set_parent() local
144 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in clk_rcg2_set_parent()
146 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), in clk_rcg2_set_parent()
151 return update_config(rcg); in clk_rcg2_set_parent()
196 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_recalc_rate() local
199 if (rcg->mnd_width) { in __clk_rcg2_recalc_rate()
200 mask = BIT(rcg->mnd_width) - 1; in __clk_rcg2_recalc_rate()
201 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in __clk_rcg2_recalc_rate()
203 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n); in __clk_rcg2_recalc_rate()
211 mask = BIT(rcg->hid_width) - 1; in __clk_rcg2_recalc_rate()
221 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_recalc_rate() local
224 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_recalc_rate()
235 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in _freq_tbl_determine_rate() local
252 index = qcom_find_src_index(hw, rcg->parent_map, f->src); in _freq_tbl_determine_rate()
292 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_select_conf() local
306 index = qcom_find_src_index(hw, rcg->parent_map, conf->src); in __clk_rcg2_select_conf()
347 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in _freq_tbl_fm_determine_rate() local
359 index = qcom_find_src_index(hw, rcg->parent_map, conf->src); in _freq_tbl_fm_determine_rate()
398 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_determine_rate() local
400 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL); in clk_rcg2_determine_rate()
406 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_determine_floor_rate() local
408 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); in clk_rcg2_determine_floor_rate()
414 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_fm_determine_rate() local
416 return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req); in clk_rcg2_fm_determine_rate()
484 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_determine_gp_rate() local
486 int mnd_max = BIT(rcg->mnd_width) - 1; in clk_rcg2_determine_gp_rate()
487 int hid_max = BIT(rcg->hid_width) - 1; in clk_rcg2_determine_gp_rate()
503 static int __clk_rcg2_configure_parent(struct clk_rcg2 *rcg, u8 src, u32 *_cfg) in __clk_rcg2_configure_parent() argument
505 struct clk_hw *hw = &rcg->clkr.hw; in __clk_rcg2_configure_parent()
506 int index = qcom_find_src_index(hw, rcg->parent_map, src); in __clk_rcg2_configure_parent()
512 *_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in __clk_rcg2_configure_parent()
517 static int __clk_rcg2_configure_mnd(struct clk_rcg2 *rcg, const struct freq_tbl *f, in __clk_rcg2_configure_mnd() argument
523 if (rcg->mnd_width && f->n) { in __clk_rcg2_configure_mnd()
524 mask = BIT(rcg->mnd_width) - 1; in __clk_rcg2_configure_mnd()
525 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure_mnd()
526 RCG_M_OFFSET(rcg), mask, f->m); in __clk_rcg2_configure_mnd()
530 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure_mnd()
531 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m)); in __clk_rcg2_configure_mnd()
544 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure_mnd()
545 RCG_D_OFFSET(rcg), mask, not2d_val); in __clk_rcg2_configure_mnd()
550 mask = BIT(rcg->hid_width) - 1; in __clk_rcg2_configure_mnd()
553 if (rcg->mnd_width && f->n && (f->m != f->n)) in __clk_rcg2_configure_mnd()
555 if (rcg->hw_clk_ctrl) in __clk_rcg2_configure_mnd()
564 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, in __clk_rcg2_configure() argument
569 ret = __clk_rcg2_configure_parent(rcg, f->src, _cfg); in __clk_rcg2_configure()
573 ret = __clk_rcg2_configure_mnd(rcg, f, _cfg); in __clk_rcg2_configure()
580 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) in clk_rcg2_configure() argument
585 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_configure()
589 ret = __clk_rcg2_configure(rcg, f, &cfg); in clk_rcg2_configure()
593 ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg); in clk_rcg2_configure()
597 return update_config(rcg); in clk_rcg2_configure()
600 static int clk_rcg2_configure_gp(struct clk_rcg2 *rcg, const struct freq_tbl *f) in clk_rcg2_configure_gp() argument
605 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_configure_gp()
609 ret = __clk_rcg2_configure_mnd(rcg, f, &cfg); in clk_rcg2_configure_gp()
613 ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg); in clk_rcg2_configure_gp()
617 return update_config(rcg); in clk_rcg2_configure_gp()
623 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_set_rate() local
628 f = qcom_find_freq_floor(rcg->freq_tbl, rate); in __clk_rcg2_set_rate()
631 f = qcom_find_freq(rcg->freq_tbl, rate); in __clk_rcg2_set_rate()
640 return clk_rcg2_configure(rcg, f); in __clk_rcg2_set_rate()
645 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_fm_set_rate() local
650 f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate); in __clk_rcg2_fm_set_rate()
664 return clk_rcg2_configure(rcg, &f_tbl); in __clk_rcg2_fm_set_rate()
676 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_set_gp_rate() local
677 int mnd_max = BIT(rcg->mnd_width) - 1; in clk_rcg2_set_gp_rate()
678 int hid_max = BIT(rcg->hid_width) - 1; in clk_rcg2_set_gp_rate()
684 ret = clk_rcg2_configure_gp(rcg, f); in clk_rcg2_set_gp_rate()
721 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_get_duty_cycle() local
724 if (!rcg->mnd_width) { in clk_rcg2_get_duty_cycle()
731 regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), ¬2d); in clk_rcg2_get_duty_cycle()
732 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in clk_rcg2_get_duty_cycle()
733 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); in clk_rcg2_get_duty_cycle()
742 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_get_duty_cycle()
757 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_set_duty_cycle() local
762 if (!rcg->mnd_width) in clk_rcg2_set_duty_cycle()
765 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_set_duty_cycle()
767 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); in clk_rcg2_set_duty_cycle()
768 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in clk_rcg2_set_duty_cycle()
769 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_set_duty_cycle()
795 ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask, in clk_rcg2_set_duty_cycle()
800 return update_config(rcg); in clk_rcg2_set_duty_cycle()
891 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_edp_pixel_set_rate() local
892 struct freq_tbl f = *rcg->freq_tbl; in clk_edp_pixel_set_rate()
897 u32 mask = BIT(rcg->hid_width) - 1; in clk_edp_pixel_set_rate()
913 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_edp_pixel_set_rate()
921 return clk_rcg2_configure(rcg, &f); in clk_edp_pixel_set_rate()
937 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_edp_pixel_determine_rate() local
938 const struct freq_tbl *f = rcg->freq_tbl; in clk_edp_pixel_determine_rate()
942 u32 mask = BIT(rcg->hid_width) - 1; in clk_edp_pixel_determine_rate()
944 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); in clk_edp_pixel_determine_rate()
963 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_edp_pixel_determine_rate()
991 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_byte_determine_rate() local
992 const struct freq_tbl *f = rcg->freq_tbl; in clk_byte_determine_rate()
993 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); in clk_byte_determine_rate()
995 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte_determine_rate()
1015 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_byte_set_rate() local
1016 struct freq_tbl f = *rcg->freq_tbl; in clk_byte_set_rate()
1018 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte_set_rate()
1025 return clk_rcg2_configure(rcg, &f); in clk_byte_set_rate()
1049 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_byte2_determine_rate() local
1051 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte2_determine_rate()
1072 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_byte2_set_rate() local
1076 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte2_set_rate()
1084 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_byte2_set_rate()
1089 if (cfg == rcg->parent_map[i].cfg) { in clk_byte2_set_rate()
1090 f.src = rcg->parent_map[i].src; in clk_byte2_set_rate()
1091 return clk_rcg2_configure(rcg, &f); in clk_byte2_set_rate()
1151 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_pixel_set_rate() local
1156 u32 mask = BIT(rcg->hid_width) - 1; in clk_pixel_set_rate()
1160 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_pixel_set_rate()
1165 if (cfg == rcg->parent_map[i].cfg) { in clk_pixel_set_rate()
1166 f.src = rcg->parent_map[i].src; in clk_pixel_set_rate()
1177 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_pixel_set_rate()
1185 return clk_rcg2_configure(rcg, &f); in clk_pixel_set_rate()
1221 * This function does ping-pong the RCG between PLLs: if we don't in clk_gfx3d_determine_rate()
1283 struct clk_rcg2 *rcg = &cgfx->rcg; in clk_gfx3d_set_rate_and_parent() local
1287 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in clk_gfx3d_set_rate_and_parent()
1288 /* On some targets, the GFX3D RCG may need to divide PLL frequency */ in clk_gfx3d_set_rate_and_parent()
1292 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); in clk_gfx3d_set_rate_and_parent()
1296 return update_config(rcg); in clk_gfx3d_set_rate_and_parent()
1323 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_set_force_enable() local
1327 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in clk_rcg2_set_force_enable()
1332 /* wait for RCG to turn ON */ in clk_rcg2_set_force_enable()
1340 pr_err("%s: RCG did not turn on\n", name); in clk_rcg2_set_force_enable()
1346 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_clear_force_enable() local
1348 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in clk_rcg2_clear_force_enable()
1355 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_force_enable_clear() local
1362 ret = clk_rcg2_configure(rcg, f); in clk_rcg2_shared_force_enable_clear()
1373 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_shared_set_rate() local
1378 f = qcom_find_freq_floor(rcg->freq_tbl, rate); in __clk_rcg2_shared_set_rate()
1381 f = qcom_find_freq(rcg->freq_tbl, rate); in __clk_rcg2_shared_set_rate()
1393 return __clk_rcg2_configure(rcg, f, &rcg->parked_cfg); in __clk_rcg2_shared_set_rate()
1424 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_enable() local
1436 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg); in clk_rcg2_shared_enable()
1440 ret = update_config(rcg); in clk_rcg2_shared_enable()
1449 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_disable() local
1455 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); in clk_rcg2_shared_disable()
1458 * Park the RCG at a safe configuration - sourced off of safe source. in clk_rcg2_shared_disable()
1459 * Force enable and disable the RCG while configuring it to safeguard in clk_rcg2_shared_disable()
1463 * is online. Therefore, the RCG can safely switch its parent. in clk_rcg2_shared_disable()
1467 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_rcg2_shared_disable()
1468 rcg->safe_src_index << CFG_SRC_SEL_SHIFT); in clk_rcg2_shared_disable()
1470 update_config(rcg); in clk_rcg2_shared_disable()
1477 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_get_parent() local
1479 /* If the shared rcg is parked use the cached cfg instead */ in clk_rcg2_shared_get_parent()
1481 return __clk_rcg2_get_parent(hw, rcg->parked_cfg); in clk_rcg2_shared_get_parent()
1488 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_set_parent() local
1490 /* If the shared rcg is parked only update the cached cfg */ in clk_rcg2_shared_set_parent()
1492 rcg->parked_cfg &= ~CFG_SRC_SEL_MASK; in clk_rcg2_shared_set_parent()
1493 rcg->parked_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in clk_rcg2_shared_set_parent()
1504 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_recalc_rate() local
1506 /* If the shared rcg is parked use the cached cfg instead */ in clk_rcg2_shared_recalc_rate()
1508 return __clk_rcg2_recalc_rate(hw, parent_rate, rcg->parked_cfg); in clk_rcg2_shared_recalc_rate()
1518 * 1. Sets rcg->parked_cfg to reflect the value at probe so that the in clk_rcg2_shared_init()
1521 * 2. Clears the force enable bit of the RCG because we rely on child in clk_rcg2_shared_init()
1522 * clks (branches) to turn the RCG on/off with a hardware feedback in clk_rcg2_shared_init()
1523 * mechanism and only set the force enable bit in the RCG when we in clk_rcg2_shared_init()
1529 * especially if the parent is shared. If this RCG is enabled at in clk_rcg2_shared_init()
1530 * boot, and the parent is turned off, the RCG will get stuck on. A in clk_rcg2_shared_init()
1531 * GDSC can wedge if is turned on and the RCG is stuck on because in clk_rcg2_shared_init()
1535 * The safest option here is to "park" the RCG at init so that the clk in clk_rcg2_shared_init()
1571 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_no_init_park() local
1577 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); in clk_rcg2_shared_no_init_park()
1603 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dfs_populate_freq() local
1609 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg); in clk_rcg2_dfs_populate_freq()
1611 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dfs_populate_freq()
1621 if (src == rcg->parent_map[i].cfg) { in clk_rcg2_dfs_populate_freq()
1622 f->src = rcg->parent_map[i].src; in clk_rcg2_dfs_populate_freq()
1623 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i); in clk_rcg2_dfs_populate_freq()
1631 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_dfs_populate_freq()
1632 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l), in clk_rcg2_dfs_populate_freq()
1637 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l), in clk_rcg2_dfs_populate_freq()
1648 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg) in clk_rcg2_dfs_populate_freq_table() argument
1657 rcg->freq_tbl = freq_tbl; in clk_rcg2_dfs_populate_freq_table()
1660 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i); in clk_rcg2_dfs_populate_freq_table()
1668 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dfs_determine_rate() local
1671 if (!rcg->freq_tbl) { in clk_rcg2_dfs_determine_rate()
1672 ret = clk_rcg2_dfs_populate_freq_table(rcg); in clk_rcg2_dfs_determine_rate()
1686 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dfs_recalc_rate() local
1689 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1690 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level); in clk_rcg2_dfs_recalc_rate()
1694 if (rcg->freq_tbl) in clk_rcg2_dfs_recalc_rate()
1695 return rcg->freq_tbl[level].freq; in clk_rcg2_dfs_recalc_rate()
1704 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level), in clk_rcg2_dfs_recalc_rate()
1707 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dfs_recalc_rate()
1715 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_dfs_recalc_rate()
1716 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1717 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m); in clk_rcg2_dfs_recalc_rate()
1720 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1721 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n); in clk_rcg2_dfs_recalc_rate()
1740 struct clk_rcg2 *rcg = data->rcg; in clk_rcg2_enable_dfs() local
1745 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val); in clk_rcg2_enable_dfs()
1759 rcg->freq_tbl = NULL; in clk_rcg2_enable_dfs()
1782 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dp_set_rate() local
1784 u32 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dp_set_rate()
1790 GENMASK(rcg->mnd_width - 1, 0), in clk_rcg2_dp_set_rate()
1791 GENMASK(rcg->mnd_width - 1, 0), &den, &num); in clk_rcg2_dp_set_rate()
1796 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_rcg2_dp_set_rate()
1802 if (cfg == rcg->parent_map[i].cfg) { in clk_rcg2_dp_set_rate()
1803 f.src = rcg->parent_map[i].src; in clk_rcg2_dp_set_rate()
1820 return clk_rcg2_configure(rcg, &f); in clk_rcg2_dp_set_rate()
1832 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dp_determine_rate() local
1838 GENMASK(rcg->mnd_width - 1, 0), in clk_rcg2_dp_determine_rate()
1839 GENMASK(rcg->mnd_width - 1, 0), &den, &num); in clk_rcg2_dp_determine_rate()