xref: /linux/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml (revision f0fd24820436d2ee4d622080216ac563f7aa59cd) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm APSS IPQ5424 Clock Controller
8
9maintainers:
10  - Varadarajan Narayanan <quic_varada@quicinc.com>
11
12description:
13  The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
14  The RCG and PLL have a separate register space from the GCC.
15
16properties:
17  compatible:
18    enum:
19      - qcom,ipq5424-apss-clk
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    items:
26      - description: Reference to the XO clock.
27      - description: Reference to the GPLL0 clock.
28
29  '#clock-cells':
30    const: 1
31
32  '#interconnect-cells':
33    const: 1
34
35required:
36  - compatible
37  - reg
38  - clocks
39  - '#clock-cells'
40  - '#interconnect-cells'
41
42additionalProperties: false
43
44examples:
45  - |
46    #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
47
48    apss_clk: clock-controller@fa80000 {
49      compatible = "qcom,ipq5424-apss-clk";
50      reg = <0x0fa80000 0x20000>;
51      clocks = <&xo_board>,
52               <&gcc GPLL0>;
53      #clock-cells = <1>;
54      #interconnect-cells = <1>;
55    };
56