Home
last modified time | relevance | path

Searched full:plls (Results 1 – 25 of 97) sorted by relevance

1234

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22 in general can provide any frequency supported by the CCU PLLs).
23 2) PLLs clocks generators (PLLs) - described in this binding file.
31 | +-|PLLs|------|- DDR controller
47 output is primarily connected to a set of CCU PLLs. There are five PLLs
51 peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
53 the PLL configuration procedure. The PLLs work as depicted on the next
77 The PLLs CLKOU
[all...]
H A Damlogic,axg-audio-clkc.yaml38 - description: input plls to generate clock signals N0
39 - description: input plls to generate clock signals N1
40 - description: input plls to generate clock signals N2
41 - description: input plls to generate clock signals N3
42 - description: input plls to generate clock signals N4
43 - description: input plls to generate clock signals N5
44 - description: input plls to generate clock signals N6
45 - description: input plls to generate clock signals N7
H A Dbaikal,bt1-ccu-div.yaml19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
24 in general can provide any frequency supported by the CCU PLLs).
25 2) PLLs clocks generators (PLLs).
34 | +-|PLLs|------|- DDR controller
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
H A Dmobileye,eyeq5-clk.yaml10 The EyeQ5 clock controller handles 10 read-only PLLs derived from the main
11 crystal clock. It also exposes one divider clock, a child of one of the PLLs.
28 - const: plls
37 Input parent clock to all PLLs. Expected to be the main crystal.
H A Dmediatek,mt8186-sys-clock.yaml14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
H A Dmediatek,mt8188-sys-clock.yaml14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
H A Dbrcm,bcm2835-cprman.txt7 of the BCM2835. There is a level of PLLs deriving from an external
9 few PLLs, and a level of mostly-generic clock generators sourcing from
H A Dmediatek,mt8195-sys-clock.yaml14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
H A Dst,nomadik.txt7 PLLs and clock gates.
23 PLL nodes: these nodes represent the two PLLs on the system,
H A Dmediatek,mt8195-clock.yaml14 PLLs -->
21 The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
H A Dmarvell,berlin.txt9 (BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
H A Drenesas,r8a73a4-cpg-clocks.txt3 The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
H A Drenesas,sh73a0-cpg-clocks.txt5 The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
/freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mt8186-sys-clock.yaml14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
H A Dmediatek,mt8195-sys-clock.yaml14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
H A Dmediatek,mt8195-clock.yaml14 PLLs -->
21 The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
H A Dmediatek,apmixedsys.txt4 The Mediatek apmixedsys controller provides the PLLs to the system.
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Doxsemi,ox820.h9 /* PLLs */
H A Dingenic,jz4740-cgu.h7 * - PLLs
H A Djz4740-cgu.h7 * - PLLs
H A Dx1000-cgu.h7 * - PLLs
H A Dmarvell,pxa910.h5 /* fixed clocks and plls */
H A Dx1830-cgu.h7 * - PLLs
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra62x-clocks.dtsi5 /* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_anadig.c194 /* Enable USB PLLs */ in anadig_attach()
198 /* Enable other PLLs */ in anadig_attach()

1234