Lines Matching full:plls

19   by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22      in general can provide any frequency supported by the CCU PLLs).
23   2) PLLs clocks generators (PLLs) - described in this binding file.
31           | +-|PLLs|------|- DDR controller
47   output is primarily connected to a set of CCU PLLs. There are five PLLs
51   peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
53   the PLL configuration procedure. The PLLs work as depicted on the next
77   The PLLs CLKOUT is then either directly connected with the corresponding