1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot #ifndef DT_CLOCK_OXSEMI_OX820_H 7*c66ec88fSEmmanuel Vadot #define DT_CLOCK_OXSEMI_OX820_H 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot /* PLLs */ 10*c66ec88fSEmmanuel Vadot #define CLK_820_PLLA 0 11*c66ec88fSEmmanuel Vadot #define CLK_820_PLLB 1 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot /* Gate Clocks */ 14*c66ec88fSEmmanuel Vadot #define CLK_820_LEON 2 15*c66ec88fSEmmanuel Vadot #define CLK_820_DMA_SGDMA 3 16*c66ec88fSEmmanuel Vadot #define CLK_820_CIPHER 4 17*c66ec88fSEmmanuel Vadot #define CLK_820_SD 5 18*c66ec88fSEmmanuel Vadot #define CLK_820_SATA 6 19*c66ec88fSEmmanuel Vadot #define CLK_820_AUDIO 7 20*c66ec88fSEmmanuel Vadot #define CLK_820_USBMPH 8 21*c66ec88fSEmmanuel Vadot #define CLK_820_ETHA 9 22*c66ec88fSEmmanuel Vadot #define CLK_820_PCIEA 10 23*c66ec88fSEmmanuel Vadot #define CLK_820_NAND 11 24*c66ec88fSEmmanuel Vadot #define CLK_820_PCIEB 12 25*c66ec88fSEmmanuel Vadot #define CLK_820_ETHB 13 26*c66ec88fSEmmanuel Vadot #define CLK_820_REF600 14 27*c66ec88fSEmmanuel Vadot #define CLK_820_USBDEV 15 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadot #endif /* DT_CLOCK_OXSEMI_OX820_H */ 30