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/linux/drivers/net/ethernet/mscc/
H A Docelot_police.c27 u32 cir = 0, cbs = 0, pir = 0, pbs = 0; in qos_policer_conf_set() local
33 pir = conf->pir; in qos_policer_conf_set()
60 pir += conf->cir; in qos_policer_conf_set()
63 if (pir == 0 && pbs == 0) { in qos_policer_conf_set()
64 /* Discard PIR frames */ in qos_policer_conf_set()
67 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
68 pir *= 3; /* 33 1/3 kbps */ in qos_policer_conf_set()
75 if (pir >= 100) { in qos_policer_conf_set()
77 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
78 pir *= 3; /* 33 1/3 fps */ in qos_policer_conf_set()
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H A Docelot_police.h29 u32 pir; /* PIR in kbps/fps */ member
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-qat_rl13 The associated attributes are: cir, pir, srv, rp, and id.
18 * Inputs: cir, pir, srv, and rp
23 * Outputs: cir, pir, srv, and rp
26 * Inputs: id, cir, and pir
93 ## Set attributes e.g. cir, pir, srv, etc
140 What: /sys/bus/pci/devices/<BDF>/qat_rl/pir
145 (RW) Peak information rate (PIR). The maximum rate that can be
147 between CIR and PIR when the device is not fully utilized by
151 PIR for that queried SLA.
163 # echo 750 > /sys/bus/pci/devices/<BDF>/qat_rl/pir
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/linux/arch/x86/include/asm/
H A Dposted_intr.h14 u32 pir[8]; /* Posted interrupt requested */ member
46 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); in pi_test_and_set_pir()
51 return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS); in pi_is_pir_empty()
99 * PIR will always be zero.
108 return test_bit(vector, (unsigned long *)pid->pir); in pi_pending_this_cpu()
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_rl.h46 * @pir: Peak information rate. Maximum rate available that the SLA can achieve.
56 * - update: cir, pir, sla_id
67 unsigned int pir; member
135 * @pir: peak information rate (PIR >= CIR)
148 u32 pir; member
H A Dadf_sysfs_rl.c29 PIR, enumerator
68 case PIR: in set_param_u()
69 data->input.pir = set; in set_param_u()
124 case PIR: in get_param_u()
125 *get = data->input.pir; in get_param_u()
250 ret = get_param_u(dev, PIR, &get); in pir_show()
267 err = set_param_u(dev, PIR, val); in pir_store()
273 static DEVICE_ATTR_RW(pir);
H A Dadf_rl.c41 if (sla_in->pir < sla_in->cir) { in validate_user_input()
43 "PIR must be >= CIR, setting PIR to CIR\n"); in validate_user_input()
44 sla_in->pir = sla_in->cir; in validate_user_input()
362 * PIR value cannot exceed the PIR assigned to parent.
377 if (sla_in->cir > rem_cir || sla_in->pir > sla_parent->pir) in can_parent_afford_sla()
389 * assigned child SLAs and if PIR can be updated
404 /* PIR of root/cluster cannot be reduced in node with assigned children */ in can_node_afford_update()
405 if (sla_in->pir < sla->pir && sla->type != RL_LEAF && cir_in_use > 0) in can_node_afford_update()
419 if (sla_in->cir > max_val || sla_in->pir > max_val) in is_enough_budget()
738 sla_in.pir = sla_in.cir; in initialize_default_nodes()
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H A Dadf_rl_admin.c32 adf_rl_calculate_pci_bw(accel_dev, sla->pir, sla->srv, false); in prep_admin_req_params()
36 adf_rl_calculate_pci_bw(accel_dev, sla->pir, sla->srv, true); in prep_admin_req_params()
41 adf_rl_calculate_slice_tokens(accel_dev, sla->pir, sla->srv); in prep_admin_req_params()
46 adf_rl_calculate_ae_cycles(accel_dev, sla->pir, sla->srv); in prep_admin_req_params()
H A Dadf_gen4_vf_mig.c159 u32 pir; member
180 src_slas[i].pir > dst_slas[j].pir) { in adf_mstate_sla_check()
340 pmig_slas->pir = sla_type_arr[i]->pir; in adf_gen4_vfmig_get_slas()
/linux/arch/x86/kernel/
H A Dirq.c383 * for checking and clearing posted interrupt request (PIR), a 256 bit field
388 * 5.Each time the IOMMU does interrupt posting to the PIR will evict the PID
398 * IOMMU's interrupt posting/atomic swap. Therefore, a copy of PIR is used
402 * as much as possible. e.g. when making a copy and clearing the PIR
403 * (assuming non-zero PIR bits are present in the entire PIR), it does:
408 static __always_inline bool handle_pending_pir(u64 *pir, struct pt_regs *regs) in handle_pending_pir() argument
415 pir_copy[i] = pir[i]; in handle_pending_pir()
421 pir_copy[i] = arch_xchg(&pir[i], 0); in handle_pending_pir()
472 * process PIR bits one last time such that handling the new interrupts in DEFINE_IDTENTRY_SYSVEC()
/linux/arch/powerpc/platforms/powernv/
H A Dopal-core.c36 /* PIR value of crashing CPU */
111 static void __init fill_prstatus(struct elf_prstatus *prstatus, int pir, in fill_prstatus() argument
118 * Overload PID with PIR value. in fill_prstatus()
119 * As a PIR value could also be '0', add an offset of '100' in fill_prstatus()
120 * to every PIR to avoid misinterpretations in GDB. in fill_prstatus()
122 prstatus->common.pr_pid = cpu_to_be32(100 + pir); in fill_prstatus()
129 if (pir == oc_conf->crashing_cpu) { in fill_prstatus()
260 thread_pir = be32_to_cpu(thdr->pir); in opalcore_append_cpu_notes()
262 pr_debug("[%04d] PIR: 0x%x, core state: 0x%02x\n", in opalcore_append_cpu_notes()
277 pr_debug("PIR 0x%x - R1 : 0x%llx, NIP : 0x%llx\n", thread_pir, in opalcore_append_cpu_notes()
H A Dopal-fadump.c462 thread_pir = be32_to_cpu(thdr->pir); in opal_fadump_build_cpu_notes()
463 pr_debug("[%04d] PIR: 0x%x, core state: 0x%02x\n", in opal_fadump_build_cpu_notes()
476 pr_debug("Crashing CPU PIR: 0x%x - R1 : 0x%lx, NIP : 0x%lx\n", in opal_fadump_build_cpu_notes()
494 pr_debug("CPU PIR: 0x%x - R1 : 0x%lx, NIP : 0x%lx\n", in opal_fadump_build_cpu_notes()
589 * CPU's PIR instead to plug the appropriate register data for in opal_fadump_trigger()
H A Dopal-hmi.c79 printk("%s CPU PIR: %08x\n", level, in print_core_checkstop_reason()
80 be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); in print_core_checkstop_reason()
H A Dopal-fadump.h59 __be32 pir; member
/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dmurata,irsd200.yaml7 title: Murata IRS-D200 PIR sensor
13 PIR sensor for human detection.
/linux/arch/powerpc/include/uapi/asm/
H A Dkvm_para.h59 __u32 pir; member
90 /* MASn, ESR, PIR, and high SPRGs */
/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_cbdr.c28 cbdr->pir = hw->reg + ENETC_SICBDRPIR; in enetc_setup_cbdr()
40 enetc_wr_reg(cbdr->pir, cbdr->next_to_clean); in enetc_setup_cbdr()
113 enetc_wr_reg(ring->pir, i); in enetc_send_cmd()
/linux/arch/powerpc/kernel/
H A Dhead_64.S63 * generic_secondary_smp_init, with PIR in r3.
65 * directed by the "start-cpu" RTS call, with PIR in r3.
71 * is at generic_secondary_smp_init, with PIR in r3.
282 * Fix PIR to match the linear numbering in the device tree.
284 * On e6500, the reset value of PIR uses the low three bits for
292 * scenario, and PIR is already set to the correct value. This
296 * at the old PIR value which state it's in, since the same value
/linux/arch/powerpc/kvm/
H A De500_emulate.c67 int pir = param & PPC_DBELL_PIR_MASK; in kvmppc_e500_emul_msgsnd() local
75 int cpir = cvcpu->arch.shared->pir; in kvmppc_e500_emul_msgsnd()
76 if ((param & PPC_DBELL_MSG_BRDCAST) || (cpir == pir)) { in kvmppc_e500_emul_msgsnd()
/linux/drivers/iio/proximity/
H A DKconfig50 tristate "Murata IRS-D200 PIR sensor"
56 Say Y here to build a driver for the Murata IRS-D200 PIR sensor.
/linux/arch/x86/kvm/vmx/
H A Dposted_intr.h21 vec = find_last_bit((unsigned long *)pi_desc->pir, 256); in pi_find_highest_vector()
/linux/drivers/net/ethernet/renesas/
H A Dsh_eth.h62 PIR, enumerator
205 /* PIR */
/linux/Documentation/virt/kvm/
H A Dvcpu-requests.rst271 role of ``vcpu->requests``. When sending a posted interrupt, PIR.ON is
273 vmx_sync_pir_to_irr() reads PIR after setting ``vcpu->mode`` to
/linux/arch/powerpc/include/asm/
H A Ddbell.h113 * by PIR/get_hard_smp_processor_id.
/linux/arch/x86/pci/
H A Dirq.c103 * $PIR format and a $IRT table is therefore there in some systems that
104 * lack a $PIR table.
113 * Unlike with the $PIR table there is no alignment guarantee.
116 * convert to the $PIR one, which we do here, except that obviously we
123 * in a $PIR table provided elsewhere. In that case this code will not
124 * be reached though as the $PIR table will have been chosen instead.

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