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/linux/drivers/pci/controller/
H A Dpcie-altera.c6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
81 #define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg)) argument
82 #define AGLX_RP_SECONDARY(pcie) \ argument
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H A Dpcie-mediatek-gen3.c3 * MediaTek PCIe host controller driver.
68 * As described in the datasheet of MediaTek PCIe Gen3 controller, wait 10ms
69 * after setting PCIE_BRG_RSTB, and before accessing PCIe internal registers.
144 /* Time in ms needed to complete PCIe reset on EN7581 SoC */
161 * @power_up: pcie power_up callback
164 * @flags: pcie device flags.
167 int (*power_up)(struct mtk_gen3_pcie *pcie);
189 * struct mtk_gen3_pcie - PCIe port information
190 * @dev: pointer to PCIe device
196 * @clks: PCIe clocks
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H A Dpcie-brcmstb.c46 /* Broadcom STB PCIe Register Offsets */
202 /* PCIe parameters */
237 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) argument
238 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA]) argument
239 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1]) argument
240 #define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG]) argument
241 #define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE]) argument
281 * The RESCAL block is tied to PCIe controller #1, regardless of the number of
282 * controllers, and turning off PCIe controller #1 prevents access to the RESCAL
295 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
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H A Dpcie-rcar-host.c3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
36 #include "pcie-rcar.h"
47 /* Structure representing the PCIe interface */
49 struct rcar_pcie pcie; member
67 * Test if the PCIe controller received PM_ENTER_L1 DLLP and in rcar_pcie_wakeup()
68 * the PCIe controller is not in L1 link state. If true, apply in rcar_pcie_wakeup()
92 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
95 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
117 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
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H A Dpcie-iproc.c25 #include "pcie-iproc.h"
92 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
139 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
151 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
230 * iProc PCIe host registers
307 /* iProc PCIe PAXB BCMA registers */
318 /* iProc PCIe PAXB registers */
334 /* iProc PCIe PAXB v2 registers */
365 /* iProc PCIe PAXC v1 registers */
374 /* iProc PCIe PAXC v2 registers */
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H A Dpcie-iproc-platform.c19 #include "pcie-iproc.h"
23 .compatible = "brcm,iproc-pcie",
26 .compatible = "brcm,iproc-pcie-paxb-v2",
29 .compatible = "brcm,iproc-pcie-paxc",
32 .compatible = "brcm,iproc-pcie-paxc-v2",
42 struct iproc_pcie *pcie; in iproc_pltfm_pcie_probe() local
48 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_pltfm_pcie_probe()
52 pcie = pci_host_bridge_priv(bridge); in iproc_pltfm_pcie_probe()
54 pcie->dev = dev; in iproc_pltfm_pcie_probe()
55 pcie->type = (uintptr_t)of_device_get_match_data(dev); in iproc_pltfm_pcie_probe()
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H A Dpcie-rcar.c3 * PCIe driver for Renesas R-Car SoCs
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
31 rcar_pci_write_reg(pcie, val, where & ~3); in rcar_rmw32()
34 int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) in rcar_pcie_wait_for_phyrdy() argument
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H A Dpcie-iproc-bcma.c15 #include "pcie-iproc.h"
28 struct iproc_pcie *pcie = dev->sysdata; in iproc_bcma_pcie_map_irq() local
29 struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); in iproc_bcma_pcie_map_irq()
37 struct iproc_pcie *pcie; in iproc_bcma_pcie_probe() local
41 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_bcma_pcie_probe()
45 pcie = pci_host_bridge_priv(bridge); in iproc_bcma_pcie_probe()
47 pcie->dev = dev; in iproc_bcma_pcie_probe()
49 pcie->type = IPROC_PCIE_PAXB_BCMA; in iproc_bcma_pcie_probe()
50 pcie->base = bdev->io_addr; in iproc_bcma_pcie_probe()
51 if (!pcie->base) { in iproc_bcma_pcie_probe()
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,eliza-qmp-gen3x1-pcie-phy
20 - qcom,eliza-qmp-gen3x2-pcie-phy
21 - qcom,glymur-qmp-gen4x2-pcie-phy
22 - qcom,glymur-qmp-gen5x4-pcie-phy
23 - qcom,hawi-qmp-gen3x2-pcie-phy
24 - qcom,hawi-qmp-gen4x1-pcie-phy
25 - qcom,kaanapali-qmp-gen3x2-pcie-phy
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/linux/drivers/pci/controller/dwc/
H A Dpcie-intel-gw.c3 * PCIe host controller driver for Intel Gateway SoCs
19 #include "pcie-designware.h"
25 /* PCIe Application logic Registers */
81 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
83 writel(val, pcie->app_base + ofs); in pcie_app_wr()
86 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
89 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
92 static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs) in pcie_rc_cfg_rd() argument
94 return dw_pcie_readl_dbi(&pcie->pci, ofs); in pcie_rc_cfg_rd()
97 static inline void pcie_rc_cfg_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_rc_cfg_wr() argument
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H A Dpcie-visconti.c3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
23 #include "pcie-designware.h"
95 /* Access registers in PCIe ulreg */
96 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
98 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
101 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
103 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
106 /* Access registers in PCIe smu */
107 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
109 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
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H A Dpcie-amd-mdb.c3 * PCIe host controller driver for AMD MDB PCIe Bridge
22 #include "pcie-designware.h"
55 * struct amd_mdb_pcie - PCIe port information
56 * @pci: DesignWare PCIe controller structure
77 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_mask() local
78 struct dw_pcie *pci = &pcie->pci; in amd_mdb_intx_irq_mask()
91 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_intx_irq_mask()
97 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_unmask() local
98 struct dw_pcie *pci = &pcie->pci; in amd_mdb_intx_irq_unmask()
111 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_intx_irq_unmask()
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H A Dpcie-uniphier.c3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
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H A Dpcie-keembay.c3 * PCIe controller driver for Intel Keem Bay
21 #include "pcie-designware.h"
70 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
72 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
76 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
86 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
90 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
94 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
99 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
104 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local
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H A DMakefile2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o
4 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
5 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
6 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
7 obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
8 obj-$(CONFIG_PCIE_ANDES_QILAI) += pcie-andes-qilai.o
9 obj-$(CONFIG_PCIE_ESWIN) += pcie-eswin.o
12 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
14 obj-$(CONFIG_PCIE_NXP_S32G) += pcie-nxp-s32g.o
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H A Dpcie-eswin.c3 * ESWIN PCIe Root Complex driver
23 #include "pcie-designware.h"
94 struct eswin_pcie *pcie) in eswin_pcie_perst_reset() argument
100 dev_err(pcie->pci.dev, "Failed to assert PERST#\n"); in eswin_pcie_perst_reset()
109 dev_err(pcie->pci.dev, "Failed to deassert PERST#\n"); in eswin_pcie_perst_reset()
116 static void eswin_pcie_assert(struct eswin_pcie *pcie) in eswin_pcie_assert() argument
120 list_for_each_entry(port, &pcie->ports, list) in eswin_pcie_assert()
122 reset_control_bulk_assert(ESWIN_NUM_RSTS, pcie->resets); in eswin_pcie_assert()
125 static int eswin_pcie_parse_port(struct eswin_pcie *pcie, in eswin_pcie_parse_port() argument
128 struct device *dev = pcie->pci.dev; in eswin_pcie_parse_port()
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H A Dpcie-armada8k.c3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
25 #include "pcie-designware.h"
73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
79 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
83 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
89 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
93 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
94 pcie->phy_count); in armada8k_pcie_enable_phys()
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H A Dpcie-al.c3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus()
31 * The DW PCIe core doesn't filter out transactions to other in al_pcie_map_bus()
92 #include "pcie-designware.h"
132 void __iomem *controller_base; /* base of PCIe unit (not DW core) */
142 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) in al_pcie_controller_readl() argument
144 return readl_relaxed(pcie->controller_base + offset); in al_pcie_controller_readl()
147 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset, in al_pcie_controller_writel() argument
150 writel_relaxed(val, pcie->controller_base + offset); in al_pcie_controller_writel()
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
26 #include "pcie-mobiveil.h"
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
72 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
86 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
87 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
88 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
103 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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H A Dpcie-layerscape-gen4.c3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up()
65 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_disable_interrupt() argument
67 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt()
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/linux/Documentation/devicetree/bindings/pci/
H A Drcar-pci-host.yaml8 title: Renesas R-Car PCIe Host
20 - const: renesas,pcie-r8a7779 # R-Car H1
23 - renesas,pcie-r8a7742 # RZ/G1H
24 - renesas,pcie-r8a7743 # RZ/G1M
25 - renesas,pcie-r8a7744 # RZ/G1N
26 - renesas,pcie-r8a7790 # R-Car H2
27 - renesas,pcie-r8a7791 # R-Car M2-W
28 - renesas,pcie-r8a7793 # R-Car M2-N
29 - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
32 - renesas,pcie-r8a774a1 # RZ/G2M
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H A Dfsl,layerscape-pcie.yaml4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
7 title: Freescale Layerscape PCIe Root Complex(RC) controller
13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
19 register available in the Freescale PCIe controller register set,
20 which can allow determining the underlying DesignWare PCIe controller version
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
30 - fsl,ls1043a-pcie
31 - fsl,ls1046a-pcie
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H A Dti,j721e-pci-ep.yaml8 title: TI J721E PCI EP (PCIe Wrapper)
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
20 - const: ti,am64-pcie-ep
21 - const: ti,j721e-pcie-ep
22 - description: PCIe EP controller in J7200
24 - const: ti,j7200-pcie-ep
25 - const: ti,j721e-pcie-ep
37 ti,syscon-pcie-ctrl:
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H A Daxis,artpec6-pcie.yaml5 $id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
8 title: Axis ARTPEC-6 PCIe host controller
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
24 - axis,artpec7-pcie-ep
32 - axis,artpec6-pcie
33 - axis,artpec6-pcie-ep
34 - axis,artpec7-pcie
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/linux/drivers/pci/controller/cadence/
H A Dpcie-sg2042.c3 * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC
13 #include "pcie-cadence.h"
18 * non-rootbus (i.e. to read/write the PCIe peripheral registers, supports
38 struct cdns_pcie *pcie; in sg2042_pcie_probe() local
52 pcie = &rc->pcie; in sg2042_pcie_probe()
53 pcie->dev = dev; in sg2042_pcie_probe()
55 platform_set_drvdata(pdev, pcie); in sg2042_pcie_probe()
61 ret = cdns_pcie_init_phy(dev, pcie); in sg2042_pcie_probe()
68 cdns_pcie_disable_phy(pcie); in sg2042_pcie_probe()
77 struct cdns_pcie *pcie = platform_get_drvdata(pdev); in sg2042_pcie_remove() local
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